Product Description
The I2C-SMBUS core implements a serial interface controller for the Inter-Integrated Circuit (I2C) bus and the System Management Bus (SMBus). The core is also suitable for the implementation of controllers for the Power Management Bus (PMBus). The core can be programmed to operate either as a bus master or a slave, and it is easy to program and integrate. An arbitration mechanism allows operation in a multiple master bus and the SMBus provisioned clock synchronization mechanism allows fast-master/slow-slave communication. Furthermore, the core detects timeout and errors to prevent bus deadlocks, and can filter out glitches on the serial line. The control, status, and data registers of the I2C-SMBUS core are accessible via an AMBA APB or a generic memory mapped interface.
The I2C-SMBUS is a microcode-free design developed for reuse in ASIC and FPGA implementations. The design uses rising-edge-triggered flip-flops only with the reset type (i.e. asynchronous and/or synchronous) being configurable at synthesis time. Furthermore, the core does not use tri-states; therefore scan insertion is straightforward.Key Features and Benefits
- Operation Modes: Master Transmitter Mode, Master Receiver Mode, Slave Receiver Mode, Slave Transmitter Mode
- I2C/SMBUS Features: Seven-bit Addressing - Byte-wide Transfers - Bus Arbitration – Clock signal (SCL) generation (in master mode) and data synchronization - START/STOP Timing detection and generation
- Special Features: Timeout/Bus error detection - Clock-Low Extension to allow fast-master slow-slave communication - Configurable glitches filter for clock and data serial lines - Bus status reporting
- Host Interfaces: 32-bit APB or 8-bit generic (8051-like) for register access
- Standards Compliance: Phillips I2C, SMBus and PMBus
Featured Documents
Device Implementation Matrix
Device utilization metrics for example implementations of this core. Contact provider for more information.
| Family | Device | Speed Grade | Tool Version | HW Validated? | Slice | LUT | BRAM | DSP48 | CMT | GTx | FMAX (Mhz) |
|---|---|---|---|---|---|---|---|---|---|---|---|
| Kintex-UP Family | XCKU3P | -3 | Vivado ML 2021.2 | 106 | 566 | 0 | 0 | 0 | 0 | 100 | |
| KINTEX-U Family | XCKU025 | -2 | Vivado ML 2021.2 | 106 | 566 | 0 | 0 | 0 | 0 | 100 | |
| ARTIX-7 Family | XC7A12T | -3 | Vivado ML 2021.2 | N | 177 | 588 | 0 | 0 | 0 | 0 | 100 |
| KINTEX-7 Family | XC7K70T | -1 | Vivado ML 2021.2 | Y | 177 | 588 | 0 | 0 | 0 | 0 | 100 |
| VIRTEX-7X Family | XC7VX330T | -1 | Vivado 2016.3 | N | 171 | 541 | 0 | 0 | 0 | 0 | 100 |
| VIRTEX-U Family | XCVU065 | -1 | Vivado 2016.3 | 100 | 543 | 0 | 0 | 0 | 0 | 100 |
IP Quality Metrics
General Information
| This Data was Current On | Oct 23, 2023 |
| Current IP Revision Number | I2C-SMBUS-1V20N00S00 |
| Date Current Revision was Released | May 24, 2022 |
| Release Date of First Version | Dec 21, 2001 |
Production Use by Xilinx Customers
| Number of Successful Xilinx Customer Production Projects | 23 |
| Can References be Made Available? | N |
Deliverables
| IP Formats Available for Purchase | Netlist, Source Code |
| Source Code Format(s) | VHDL, Verilog |
| High-Level Model Included? | N |
| Integration Testbench Provided | Y |
| Integration Test Bench Format(s) | Verilog |
| Code Coverage Report Provided? | Y |
| Functional Coverage Report Provided? | Y |
| UCFs Provided? | UCF |
| Commercial Evaluation Board Available? | N |
| Software Drivers Provided? | Y |
| Driver OS Support | Bare Metal Drivers |
Implementation
| Code Optimized for Xilinx? | N |
| Synthesis Software Tools Supported/Version | Vivado Synthesis; Synplicity Synplify; Mentor Precision; Xilinx XST |
| Static Timing Analysis Performed? | Y |
| AXI Interfaces | AXI4-Lite |
| IP-XACT Metadata Included? | N |
Verification
| Is a Document Verification Plan Available? | Yes, document only plan |
| Test Methodology | Directed Testing |
| Assertions | Y |
| Coverage Metrics Collected | Code |
| Timing Verification Performed? | Y |
| Timing Verification Report Available | N |
| Simulators Supported | Mentor ModelSIM; Mentor Questa; Cadence NC-Sim |
Hardware Validation
| Validated on FPGA | Y |
| Hardware Validation Platform Used | Propriatory hardware board based on Spartan-3 |
| Industry Standard Compliance Testing Passed | N |
| Specific Compliance Test | N/A |