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DI2CM - I2C Bus Controller Master

Product Description

The I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of short distance data transmission between many devices. The DI2CM core provides an interface between a microprocessor / microcontroller and an I2C bus. It can work as a master transmitter or a master receiver, depending on a working mode determined by the microprocessor/microcontroller. The DI2CM core incorporates all features required by the latest I2C specification, including clock synchronization, arbitration, multi-master systems and High-speed transmission mode. A built-in timer allows operation from a wide range of the clk frequencies. The DI2CM is a technology independent design and can be implemented in various process technologies.

Key Features and Benefits

  • Scan test ready
  • No internal tri-states
  • Static synchronous design with positive edge clocking and synchronous reset
  • Fully synthesizable
  • User-defined timing (data setup, start setup, start hold, etc.)
  • Host side interface dedicated for microproces-sors / microcontrollers
  • Built-in 8-bit timer for data transfers speed adjusting
  • Interrupt generation
  • Support for both 7-bit and 10-bit addressing formats on the I2C bus
  • Support for multi-master systems
  • Arbitration and clock synchronization
  • Support for all transmission speeds - Standard (up to 100 kb/s), Fast (up to 400 kb/s), Fast Plus (up to 1 Mb/s) and High Speed (up to 3,4 Mb/s)
  • Master operation (Master transmitter, Master receiver)
  • Conforms to v.3.0 of the I2C specification

What's Included

  • 3 months maintenance
  • Active-HDL automatic simulation macros
  • Datasheet
  • Delivery the IP Core updates, minor and major versions changes
  • Delivery the documentation updates
  • Example application
  • HDL core specification
  • IP Core implementation support
  • Installation notes
  • ModelSim automatic simulation macros
  • Phone & email support
  • Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF netlist
  • Synthesis scripts
  • Technical documentation
  • Technical support
  • Tests with reference responses
  • VHDL & VERILOG test bench environment

Featured Documents

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
Zynq-UP-MPSoC Family XCZU19EG -3 Vivado 2019.1 Y 40 223 0 0 0 0 550
KINTEX-U Family XCKU025 -3 Vivado 2019.1 Y 43 223 0 0 0 0 530
Spartan-7 Family XC7S75 -3 Vivado 2019.1 Y 69 224 0 0 0 0 520
KINTEX-7 Family XC7K70T -3 ISE 14.4 Y 67 207 0 0 0 0 511
ARTIX-7 Family XC7A100T -3 ISE 14.4 Y 79 174 0 0 0 0 327
Zynq-7000 Family XC7Z010 -3 Vivado 2019.1 Y 79 249 0 0 0 0 350
Spartan 6 Family XC6SLX4 -4 ISE 14.4 Y 75 173 0 0 0 0 270
SPARTAN3E Family XC3S100E -5 ISE 14.4 Y 190 264 0 0 0 0 162
KINTEX-U Family XCKU035 -3 Vivado 2017.1 Y 42 222 0 0 0 0 520
VIRTEX-U Family XCVU065 -3 Vivado 2015.1 Y 44 246 0 0 0 0 500

IP Quality Metrics

General Information

This Data was Current On Jan 10, 2022
Current IP Revision Number 4.01
Date Current Revision was Released Jan 04, 2011
Release Date of First Version Mar 04, 2000

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 10
Can References be Made Available? N


IP Formats Available for Purchase Netlist, Source Code
Source Code Format(s) VHDL, Verilog
High-Level Model Included? N
Integration Testbench Provided Y
Integration Test Bench Format(s) Verilog, VHDL
Code Coverage Report Provided? Y
Functional Coverage Report Provided? N
UCFs Provided? UCF
Commercial Evaluation Board Available? N
Software Drivers Provided? Y
Driver OS Support no


Code Optimized for Xilinx? N
Custom FPGA Optimization Techniques none
Synthesis Software Tools Supported/Version Xilinx XST; Synplicity Synplify; Mentor Precision; Other
Static Timing Analysis Performed? Y
IP-XACT Metadata Included? N


Is a Document Verification Plan Available? Executable and documented plan
Test Methodology Both
Assertions N
Coverage Metrics Collected Code, Functional, Assertion
Timing Verification Performed? Y
Timing Verification Report Available Y
Simulators Supported Cadence NC-Sim; Cadence IUS; Mentor ModelSIM

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used FPGA
Industry Standard Compliance Testing Passed N
Test Date Jun 20, 2000
Are Test Results Available? Y