Product Description
The DLIN is a soft core of the Local Interconnect Network (LIN). This interface is a serial communication protocol, designed primarily to be used in automotive applications. Compared to CAN, LIN is slower, but thanks to its simplicity, is much more cost effective. Our Core is ideal for a communication in intelligent sensors and actuators, where the bandwidth and versatility of CAN is not required. The DLIN core provides an interface between a microprocessor/microcontroller and a LIN bus. It can work as master or slave LIN node, depending on a work mode, determined by the microprocessor/microcontroller. DCD's controller supports transmission speed between 1 and 20kb/s, which allows it to transmit and receive LIN messages compatible to LIN 1.3. LIN 2.1 and the newest 2.2. The reported information status includes the type and condition of transfer operations being performed by the DLIN, as well as a wide range of LIN error conditions (overrun, framing, parity, timeout). Our Core includes programmable timer, which allows to detect timeout and synchronization error. The DLIN is described at RTL level, empowering the target use in FPGA and ASIC technologies.
Key Features and Benefits
- “Break-in-data” support
- Extended error detection
- Time-out detection
- Master and Slave work mode
- Data rate between 1Kbit/s and 20 Kbit/s
- Automatic Re-synchronization
- Automatic LIN Header handling
- Conforms with LIN 1.2, LIN 2.1 and LIN 2.2 specification
Device Implementation Matrix
Device utilization metrics for example implementations of this core. Contact provider for more information.
| Family | Device | Speed Grade | Tool Version | HW Validated? | Slice | LUT | BRAM | DSP48 | CMT | GTx | FMAX (Mhz) |
|---|---|---|---|---|---|---|---|---|---|---|---|
| VIRTEX-UP Family | XCVU13P | -2 | Vivado ML 2023.1 | Y | 495 | 783 | 0 | 0 | 0 | 0 | 512 |
| KINTEX-7 Family | XC7K410T | -1 | Vivado ML 2023.1 | Y | 495 | 838 | 0 | 0 | 0 | 0 | 285 |
| ARTIX-7 Family | XC7A200T | -3 | Vivado ML 2023.1 | Y | 495 | 830 | 0 | 0 | 0 | 0 | 263 |
| Zynq-7000 Family | XC7Z010 | -3 | Vivado 2019.1 | Y | 0 | 620 | 0 | 0 | 0 | 0 | 263 |
| Spartan 6 Family | XC6SLX16 | -3 | ISE 14.4 | Y | 167 | 511 | 0 | 0 | 0 | 0 | 127 |
| VIRTEX-U Family | XCVU080 | -3 | Vivado 2015.4 | Y | 0 | 539 | 0 | 0 | 0 | 0 | 330 |
| KINTEX-U Family | XCKU035 | -3 | Vivado 2015.4 | Y | 0 | 516 | 0 | 0 | 0 | 0 | 330 |
IP Quality Metrics
General Information
| This Data was Current On | Nov 15, 2023 |
| Current IP Revision Number | 1.03 |
| Date Current Revision was Released | Dec 13, 2013 |
| Release Date of First Version | Sep 12, 2008 |
Production Use by Xilinx Customers
| Number of Successful Xilinx Customer Production Projects | 2 |
| Can References be Made Available? | N |
Deliverables
| IP Formats Available for Purchase | Netlist, Source Code |
| Source Code Format(s) | VHDL, Verilog |
| High-Level Model Included? | N |
| Integration Testbench Provided | Y |
| Integration Test Bench Format(s) | VHDL, Verilog |
| Code Coverage Report Provided? | Y |
| Functional Coverage Report Provided? | N |
| UCFs Provided? | UCF |
| Commercial Evaluation Board Available? | N |
| Software Drivers Provided? | Y |
| Driver OS Support | - |
Implementation
| Code Optimized for Xilinx? | N |
| Custom FPGA Optimization Techniques | - |
| Synthesis Software Tools Supported/Version | Xilinx XST; Synplicity Synplify; Mentor Precision |
| Static Timing Analysis Performed? | Y |
| IP-XACT Metadata Included? | N |
Verification
| Is a Document Verification Plan Available? | Executable and documented plan |
| Test Methodology | Both |
| Assertions | N |
| Coverage Metrics Collected | Code, Functional, Assertion |
| Timing Verification Performed? | Y |
| Timing Verification Report Available | Y |
| Simulators Supported | Cadence NC-Sim; Cadence IUS; Mentor ModelSIM |
Hardware Validation
| Validated on FPGA | Y |
| Hardware Validation Platform Used | FPGA |
| Industry Standard Compliance Testing Passed | N |
| Specific Compliance Test | own |
| Test Date | Sep 11, 2008 |
| Are Test Results Available? | Y |