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CAN 2.0B and CAN-FD Controller

  • Part Number: CAN-CTRL
  • Vendor: CAST, Inc.
  • Alliance Program Tier: Certified

Product Description

Implements a CAN protocol bus controller that performs serial communication according to the CAN 2.0A, 2.0B, and the ISO/Bosch CAN FD Flexible Data-Rate specifications. Additionally, it supports time-triggered (TTCAN) operations and optional time stamps. The CAN-CTRL core is easy to use and integrate featuring programmable interrupts, data and baud rates; a configurable number of independently programmable acceptance filters; and a generic processor interface or optionally an AMBA-APB interface. It implements a flexible buffering scheme, allowing fine-tuning of the core size to the requirements of each specific application. The number of receive and transmitting buffers is synthesis-time configurable. Two types of transmit buffers are implemented: a high-priority primary transmit buffer (PTB) and a lower-priority secondary transmit buffer (STB). The PTB can store one message, while the number of included buffer slots for the STB is synthesis-time configurable 0 to 16 slots. Moreover, an optional wrapper instantiating multiple CAN controller cores easies integration in cases where multiple bus-nodes need to be controlled by the same host processor. The core implements functionality similar to the Philips SJA1000 working with its PeliCAN mode extensions, providing error analysis, diagnosis, system maintenance and optimization features.


Key Features and Benefits

  • 32-bit host-controller generic interface and optional AMBA-APB
  • Buffers can be implemented as Flip-Flops, or RAM
  • Configurable number of lower-priority transmit buffers
  • Configurable number of receive buffers (2 to 31)
  • Flexible programmable interrupt sources
  • Multiple times production proven and plug-fest tested
  • One high-priority transmit buffer
  • Optimized for AUTOSAR and SAE J1939
  • Programmable baud rate prescaler (1/2 up to 1/256)
  • Programmable data rate up to 1 Mbps for CAN2.0 and several Mbps for CAN-FD
  • Standard and Extended Data and Remote Frames
  • Supports CAN 2.0 & CAN-FD including TTCAN (ISO 11898-4 level 1)
  • Three independent programmable internal 29-bit acceptance filters

Featured Documents

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
ARTIX-7 Family XC7A15T -2 Vivado 2016.4 Y 545 1704 1 0 0 0 100
VIRTEX-7X Family XC7VX330T -3 Vivado 2013.3 N 738 2194 0 0 0 0 170
KINTEX-U Family XCKU040 -2 Vivado 2014.4 N 245 1451 0 0 0 0 80
KINTEX-U Family XCKU060 -2 Vivado 2016.4 N 332 1660 1 2 0 0 200
VIRTEX-U Family XCVU080 -2 Vivado 2016.4 N 313 1660 1 2 0 0 200

IP Quality Metrics

General Information

This Data was Current On Sep 25, 2017
Current IP Revision Number 6x19n00s00
Date Current Revision was Released May 05, 2017
Release Date of First Version Feb 18, 2000

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 80
Can References be Made Available? Y

Deliverables

IP Formats Available for Purchase Netlist, Source Code
Source Code Format(s) VHDL, Verilog
High-Level Model Included? N
Integration Testbench Provided Y
Integration Test Bench Format(s) Verilog, VHDL
Code Coverage Report Provided? Y
Functional Coverage Report Provided? Y
UCFs Provided? UCF
Commercial Evaluation Board Available? N
Software Drivers Provided? N
Driver OS Support N/A

Implementation

Code Optimized for Xilinx? Y
Standard FPGA Optimization Techniques Inference
Custom FPGA Optimization Techniques BRAMs
Synthesis Software Tools Supported/Version Mentor Precision; Synplicity Synplify; Xilinx XST
Static Timing Analysis Performed? N
AXI Interfaces AXI4-Lite
IP-XACT Metadata Included? N

Verification

Is a Document Verification Plan Available? Yes, document only plan
Test Methodology Both
Assertions N
Coverage Metrics Collected Code
Timing Verification Performed? Y
Timing Verification Report Available Y
Simulators Supported Mentor Questa; Mentor ModelSIM; Cadence NC-Sim

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used Kintex7
Industry Standard Compliance Testing Passed N
Specific Compliance Test N/A
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