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  3. CAN 2.0, CAN FD, & CAN-XL Controller

CAN 2.0, CAN FD, & CAN-XL Controller

  • Part Number: CAN-CTRL
  • Vendor: CAST, Inc.
  • Partner Tier: Elite Certified
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Product Description

Implements a CAN bus controller that performs serial communication according to the CAN 2.0, CAN FD, and CAN XL specifications. The CAN-CTRL core is easy to use and integrate, featuring programmable interrupts, data and baud rates; a configurable number of independently programmable acceptance filters; and a generic processor interface or optionally an AMBA APB, or AHB-Lite interface. The number of receive buffers is synthesis-time configurable. Two types of transmit buffers are implemented: a high-priority primary transmit buffer (PTB) and a lower-priority secondary transmit buffer (STB). The PTB can store one message, while the number of included buffer slots for the STB is synthesis-time configurable. The transmit buffer can operate in FIFO or priority mode. The core implements functionality similar to the Philips SJA1000 working with its PeliCAN mode extensions, providing error analysis, diagnosis, system maintenance, and optimization features. The CAN-CTRL is available in two versions: Normal, and Safety-Enhanced. The Safety-Enhanced version implements ECC for SRAMs protection and uses spatial redundancy for protecting the inner logic of the core. The deliverables for this version include a Safety Manual (SAM), a Failure Modes, Effects and Diagnostics Analysis (FMEDA), and the ISO-26262 ASIL-B Ready certificate, issued by SGS-TÜV Saar GmbH. The core is extensively verified, proven in several plug fests and a large number of production designs.

Key Features and Benefits

  • Optional Safety Enhanced Version implements ECC for SRAM and spatial redundancy for inner logic protection, and it is ISO-26262 ASIL-D Ready.
  • Supports CAN 2.0 & CAN-FD (ISO 11898-1.2015), TTCAN (ISO 11898-4 level 1), and CAN XL (CiA 601-1)
  • Optimized for AUTOSAR and SAE J1939
  • Enhanced Functionality: Reports bus errors and supports Listen-Only and Loop-Back modes, enabling traffic analysis, bit-rate detection, and shelf-testing.
  • Configuration Options: Number of Rx & Tx buffers, number of acceptance filters, number of CAN nodes and host bus type (AHB-Lite, APB or generic uP).
  • Maturity: Multiple times production proven. Proven with different transceivers and tested in CAN-FD plug-fests

Featured Documents

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
Kintex-UP Family XCKU3P -3 Vivado 2018.3 N 298 1559 1 0 0 0 80
ARTIX-7 Family XC7A12T -3 Vivado 2018.3 Y 517 1531 1 0 0 0 80
KINTEX-U Family XCKU035 -2 Vivado 2018.3 Y 275 1560 1 0 0 0 80

IP Quality Metrics

General Information

This Data was Current On Oct 23, 2023
Current IP Revision Number 7x10n00s00
Date Current Revision was Released Mar 17, 2020
Release Date of First Version Feb 18, 2000

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 120
Can References be Made Available? Y

Deliverables

IP Formats Available for Purchase Netlist, Source Code
Source Code Format(s) VHDL, Verilog
High-Level Model Included? N
Integration Testbench Provided Y
Integration Test Bench Format(s) Verilog, VHDL
Code Coverage Report Provided? Y
Functional Coverage Report Provided? Y
UCFs Provided? UCF
Commercial Evaluation Board Available? N
Software Drivers Provided? N
Driver OS Support N/A

Implementation

Code Optimized for Xilinx? Y
Standard FPGA Optimization Techniques Inference
Custom FPGA Optimization Techniques BRAMs
Synthesis Software Tools Supported/Version Mentor Precision; Synplicity Synplify; Xilinx XST
Static Timing Analysis Performed? N
AXI Interfaces AXI4-Lite
IP-XACT Metadata Included? N

Verification

Is a Document Verification Plan Available? Yes, document only plan
Test Methodology Both
Assertions N
Coverage Metrics Collected Code
Timing Verification Performed? Y
Timing Verification Report Available Y
Simulators Supported Mentor Questa; Mentor ModelSIM; Cadence NC-Sim

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used Kintex7
Industry Standard Compliance Testing Passed N
Specific Compliance Test N/A