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D68000-BDM

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Product Description

D68000-BDM soft core is binary-compatible with an industry-standard 68000 32-bit microprocessor. It has a 16-bit data bus and a 24-bit address data bus. Of course, the code is compatible with MC68008, upward compatible with MC68010 virtual extensions, and MC68020 32-bit implementation of the architecture. Our efficient IP Core has an improved instruction set, which allows the execution of the program with higher performance than a standard 68000 core. D68000-BDM is delivered with a fully automated test bench and complete set of tests, allowing easy package validation at each stage of the SoC design flow.

You might also like: - D68000-CPU32 - https://www.dcd.pl/product/d68000-cpu32-2/ - D68000-CPU32+ - https://www.dcd.pl/product/d68000-cpu32-plus/

Key Features and Benefits

  • USB, Ethernet, I2C, SPI, UART, CAN, LIN, HDLC, Smart Card interfaces available
  • Static synchronous design
  • Fully synthesizable
  • M6800 family synchronous interface: 3- and 2- wire bus arbitration; Supervisor and user modes
  • Memory interface includes: Up to 4 GB of address space; 16-bit data bus; Asynchronous bus control
  • Interrupt controller: 7 priority levels interrupt controller; Unlimited number of virtual interrupt sources; Vectored and auto-vectored modes
  • Arithmetic Logic Unit includes: 8,16,32-bit arithmetic & logical operations; 16×16 bit signed and unsigned multiplication; 32/16 bit signed and unsigned division; Boolean operations
  • 5 data types supported: bits; BCD; bytes, words and long words
  • Immediate data: Immediate; Quick immediate
  • Absolute data: Absolute short; Absolute long
  • PC relative: Relative with offset; Relative with index and offset
  • Indirect: Register indirect; Postincrement register indirect; Predecrement register indirect; Register indirect with offset; Indexed register indirect with offset
  • Direct: Data register direct; Address register direct
  • 14 addressing modes:
  • 32 bit data and address registers
  • Bus cycle timings identical to 68000
  • Shorter effective address calculation time
  • Idle cycles removed to improve performance
  • Optimized shifts and rotations
  • DIVS, DIVU take 28 clock periods
  • MULS, MULU take 28 clock periods
  • Software compatible with 68000 industry standard

Featured Documents

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
KINTEX-7 Family XC7K70T -1 Vivado ML 2023.2 Y 1265 5724 0 0 0 0 100
VIRTEX-7X Family XC7VX330T -3 Vivado 2019.1 Y 2710 7020 0 0 0 0 101
Zynq-7000 Family XC7Z010 -3 Vivado 2019.1 Y 1867 6725 0 0 0 0 115

IP Quality Metrics

General Information

This Data was Current On Jan 24, 2024
Current IP Revision Number 1.22
Date Current Revision was Released Jan 18, 2016
Release Date of First Version Jun 17, 2003

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 5
Can References be Made Available? N

Deliverables

IP Formats Available for Purchase Netlist, Source Code
Source Code Format(s) VHDL, Verilog
High-Level Model Included? N
Integration Testbench Provided Y
Integration Test Bench Format(s) VHDL, Verilog
Code Coverage Report Provided? Y
Functional Coverage Report Provided? N
UCFs Provided? UCF
Commercial Evaluation Board Available? N
Software Drivers Provided? Y
Driver OS Support -

Implementation

Code Optimized for Xilinx? N
Custom FPGA Optimization Techniques -
Synthesis Software Tools Supported/Version Xilinx XST; Synplicity Synplify; Mentor Precision
Static Timing Analysis Performed? Y
IP-XACT Metadata Included? N

Verification

Is a Document Verification Plan Available? Executable and documented plan
Test Methodology Both
Assertions N
Coverage Metrics Collected Code, Functional, Assertion
Timing Verification Performed? Y
Timing Verification Report Available Y
Simulators Supported Cadence NC-Sim; Cadence IUS; Mentor ModelSIM

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used FPGA
Industry Standard Compliance Testing Passed N
Specific Compliance Test own
Test Date Jun 16, 2003
Are Test Results Available? Y