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D68000 - 68000 Compatible Microprocessor

Product Description

The D68000 soft core is binary-compatible with the industry standard 68000 32-bit microcoprocessor. It has a 16-bit data bus and a 24-bit address data bus. Of course, its code is compatible with the MC68008, upward code compatible with MC68010 virtual extensions and the MC68020 32-bit implementation of the architecture. Our efficient IP Core has an improved instructions set, which allows to execute the program with higher performance, than a standard 68000 core. The D68000 is delivered with fully automated test-bench and complete set of tests, which allow easy package validation at each stage of SoC design flow.

Key Features and Benefits

  • Static synchronous design
  • Fully synthesizable
  • M6800 family synchronous interface
  • Memory interface includes: Up to 4 GB of address space; 16-bit data bus; Asynchronous bus control
  • Interrupt controller: 7 priority levels interrupt controller; Unlimited number of virtual interrupt sources; Vectored and auto-vectored modes
  • Arithmetic Logic Unit includes: 8,16,32-bit arithmetic & logical operations; 16x16 bit signed and unsigned multiplication; 32/16 bit signed and unsigned division; Boolean operations
  • 5 data types supported: bits; BCD; bytes, words and long words
  • 14 addressing modes: Direct; Indirect; PC relative; Absolute data; Immediate data;
  • 32 bit data and address registers
  • Bus cycle timings identical to 68000
  • Shorter effective address calculation time
  • Idle cycles removed to improve performance
  • Optimized shifts and rotations
  • DIVS, DIVU take 28 clock periods
  • MULS, MULU take 28 clock periods
  • Software compatible with 68000 industry standard

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
KINTEX-7 Family XC7K70T -3 ISE 14.4 Y 2510 6999 0 0 0 0 107
VIRTEX-7X Family XC7VX330T -3 ISE 14.4 Y 2710 7020 0 0 0 0 101
Zynq-7000 Family XC7Z010 -3 Vivado 2015.4 Y 1867 6725 0 0 0 0 115
Spartan 6T Family XC6SLX45T -3 ISE 14.4 Y 2300 6980 0 0 0 0 79

IP Quality Metrics

General Information

This Data was Current On Jan 22, 2018
Current IP Revision Number 1.22
Date Current Revision was Released Jan 18, 2016
Release Date of First Version Jun 17, 2003

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 5
Can References be Made Available? N


IP Formats Available for Purchase Netlist, Source Code
Source Code Format(s) VHDL, Verilog
High-Level Model Included? N
Integration Testbench Provided Y
Integration Test Bench Format(s) VHDL, Verilog
Code Coverage Report Provided? Y
Functional Coverage Report Provided? N
UCFs Provided? UCF
Commercial Evaluation Board Available? N
Software Drivers Provided? Y
Driver OS Support -


Code Optimized for Xilinx? N
Custom FPGA Optimization Techniques -
Synthesis Software Tools Supported/Version Xilinx XST; Synplicity Synplify; Mentor Precision
Static Timing Analysis Performed? Y
IP-XACT Metadata Included? N


Is a Document Verification Plan Available? Executable and documented plan
Test Methodology Both
Assertions N
Coverage Metrics Collected Code, Functional, Assertion
Timing Verification Performed? Y
Timing Verification Report Available Y
Simulators Supported Cadence NC-Sim; Cadence IUS; Mentor ModelSIM

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used FPGA
Industry Standard Compliance Testing Passed N
Specific Compliance Test own
Test Date Jun 16, 2003
Are Test Results Available? Y
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