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logiSPI SPI to AXI4 Controller Bridge

Product Description

The logiSPI SPI to AXI-4 Controller Bridge IP core from Xylon's logicBRICKS IP library enables easy inter-chip board-level interfacing between virtually any microcontroller (MCU) and Xilinx Zynq-7000 SoC and FPGAs through the Serial Peripheral Interface (SPI) bus. The SPI is a full-duplex synchronous four-wire serial interface between a single bus master, and one or more bus slave devices.

The logiSPI IP core enables easy implementations of Xilinx FPGA/SoC companion chips that expand the capabilities of the embedded host processor by adding missing host features and by offloading high-speed processing tasks. It works as the SPI Slave controller and a 32-bit master controller on the ARM AMBA Advanced eXtensible Interface (AXI-4) on-chip bus. It accepts and decodes a number of command SPI telegrams and allows the MCU to control peripherals implemented in the Zynq-7000 SoC or FPGA, or communicate with on-chip processors. Implemented bursting mechanism allows for large (2Kbytes) data transfers between on-chip and off-chip memories controlled by Xilinx programmable devices.

Key Features and Benefits

  • Bridge controller between the Serial Peripheral Interface (SPI) bus and the Advanced eXtensible Interface (AXI4) on-chip bus
  • Works as a Slave controller on the SPI bus, and a master controller on AXI4
  • Enables full-duplex communication (MSB first) between an external SPI Master controller and SoC/FPGA peripherals, processors, on- and off- chip memories
  • Supports different SPI telegrams
  • Supports four signals interface
  • Optional transfer status signlas, SPI telegrams acknowledgment and Slave reset mechanisms
  • Prepared for Xilinx Vivado and ISE Design Suites

Featured Documents

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
KINTEX-7 Family XC7K70T -2 ISE 14.4 Y 278 706 0 0 0 0 270
ARTIX-7 Family XC7A200T -7 ISE 14.4 Y 264 703 0 0 0 0 260
Zynq-7000 Family XC7Z020 -1 Vivado 2017.4 Y 243 618 0 0 0 0 100
Spartan 6T Family XC6SLX45T -3 ISE 14.4 Y 278 729 0 0 0 0 200

IP Quality Metrics

General Information

This Data was Current On Oct 18, 2018
Current IP Revision Number 3.2
Date Current Revision was Released Oct 17, 2018
Release Date of First Version Apr 18, 2013

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 13
Can References be Made Available? N


IP Formats Available for Purchase Bitstream, Netlist, Source Code
Source Code Format(s) VHDL
High-Level Model Included? N
Integration Testbench Provided N
Code Coverage Report Provided? N
Functional Coverage Report Provided? N
UCFs Provided? N
Software Drivers Provided? N


Code Optimized for Xilinx? Y
Standard FPGA Optimization Techniques Inference, Instantiation
Synthesis Software Tools Supported/Version Xilinx XST
Static Timing Analysis Performed? Y
AXI Interfaces AXI4
IP-XACT Metadata Included? N


Is a Document Verification Plan Available? No
Test Methodology Directed Testing
Assertions Y
Coverage Metrics Collected Assertion
Timing Verification Performed? Y
Timing Verification Report Available Y
Simulators Supported Mentor ModelSIM

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used Xylon logiCRAFT-CC
Industry Standard Compliance Testing Passed N
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