The logiSPI SPI to AXI-4 Controller Bridge IP core from Xylon's logicBRICKS IP library enables easy inter-chip board-level interfacing between virtually any microcontroller (MCU) and Xilinx Zynq-7000 SoC and FPGAs through the Serial Peripheral Interface (SPI) bus. The SPI is a full-duplex synchronous four-wire serial interface between a single bus master, and one or more bus slave devices.
The logiSPI IP core enables easy implementations of Xilinx FPGA/SoC companion chips that expand the capabilities of the embedded host processor by adding missing host features and by offloading high-speed processing tasks. It works as the SPI Slave controller and a 32-bit master controller on the ARM AMBA Advanced eXtensible Interface (AXI-4) on-chip bus. It accepts and decodes a number of command SPI telegrams and allows the MCU to control peripherals implemented in the Zynq-7000 SoC or FPGA, or communicate with on-chip processors. Implemented bursting mechanism allows for large (2Kbytes) data transfers between on-chip and off-chip memories controlled by Xilinx programmable devices.
Key Features and Benefits
- Bridge controller between the Serial Peripheral Interface (SPI) bus and the Advanced eXtensible Interface (AXI4) on-chip bus
- Works as a Slave controller on the SPI bus, and a master controller on AXI4
- Enables full-duplex communication (MSB first) between an external SPI Master controller and SoC/FPGA peripherals, processors, on- and off- chip memories
- Supports different SPI telegrams
- Supports four signals interface
- Optional transfer status signlas, SPI telegrams acknowledgment and Slave reset mechanisms
- Prepared for Xilinx Vivado and ISE Design Suites