Product Description
The logiWIN IP core accepts a streaming video input, decodes it and converts into the RGB format. The input video can be real-time scaled, de-interlaced, cropped and positioned on the video display. Captured video can be processed by various IP cores and displayed by a graphics controller IP, i.e. the logiCVC-ML Compact Multilayer Video Controller LCD display controller IP core from Xylon. The logiWIN integrates high-quality anti-aliasing algorithm that guarantees high picture quality without visible artifacts. The core is fully embedded into Xilinx Vivado and ISE Design Suites, and its usage does not require skills beyond general Xilinx tools knowledge. Parametrizable VHDL design allows tuning of slice consumption and features set through implementation tools GUI interface. Instantiations of multiple logiWIN IPs enable processing of multiple video inputs within a single Xilinx FPGA device. To enable an easy IP evaluation, Xylon offers a number of free reference designs for the most popular Zynq-7000 SoC based development boards.
Key Features and Benefits
- Double or triple buffering for video flicker prevention
- Provides Bob ad Weave de-interlacing algorithms
- Maximum input and output resolutions are 2048x2048
- Supports Pixel Alpha blending
- Supported busses: AMBA AXI4 and Xylon XMB
- Video input cropping and smooth image positioning
- Image color enhancements: brightness, contrast, hue, saturation
- Output video formats: RGB ad YCbCr
- Input video formats: RGB, ITU656 (PAL/NTSC), ITU1120, YUV4:2:2
- Real-time video scale-up and scale down
Featured Documents
Device Implementation Matrix
Device utilization metrics for example implementations of this core. Contact provider for more information.
| Family | Device | Speed Grade | Tool Version | HW Validated? | Slice | LUT | BRAM | DSP48 | CMT | GTx | FMAX (Mhz) |
|---|---|---|---|---|---|---|---|---|---|---|---|
| Zynq-UP-MPSoC Family | XCZU9EG | -2 | Vivado ML 2021.1 | Y | 0 | 2393 | 6 | 8 | 0 | 0 | 240 |
| VERSAL_AI_CORE Family | XCVC1902 | -1 | Vivado 2019.1 | 0 | 2993 | 6 | 8 | 0 | 0 | 200 | |
| Zynq-7000 Family | XC7Z020 | -1 | Vivado 2018.3 | Y | 732 | 1625 | 4 | 11 | 0 | 0 | 170 |
| Spartan 6 Family | XC6SLX75 | -3 | ISE 14.4 | Y | 427 | 834 | 3 | 6 | 0 | 0 | 200 |
| VIRTEX6LXT Family | XC6VLX75T | -3 | ISE 14.4 | Y | 446 | 823 | 3 | 6 | 0 | 0 | 280 |
IP Quality Metrics
General Information
| This Data was Current On | Feb 16, 2022 |
| Current IP Revision Number | 5.2.1 |
| Date Current Revision was Released | Feb 06, 2020 |
| Release Date of First Version | Mar 12, 2009 |
Production Use by Xilinx Customers
| Number of Successful Xilinx Customer Production Projects | 55 |
| Can References be Made Available? | N |
Deliverables
| IP Formats Available for Purchase | Bitstream, Netlist, Source Code |
| Source Code Format(s) | VHDL |
| High-Level Model Included? | N |
| Integration Testbench Provided | Y |
| Integration Test Bench Format(s) | VHDL |
| Code Coverage Report Provided? | N |
| Functional Coverage Report Provided? | N |
| UCFs Provided? | UCF |
| Commercial Evaluation Board Available? | Y |
| FPGA Used on Board | Spartan-6 |
| Software Drivers Provided? | Y |
| Driver OS Support | Linux |
Implementation
| Code Optimized for Xilinx? | Y |
| Standard FPGA Optimization Techniques | Inference, Instantiation |
| Synthesis Software Tools Supported/Version | Xilinx XST |
| Static Timing Analysis Performed? | Y |
| AXI Interfaces | AXI4, AXI4-Lite |
| IP-XACT Metadata Included? | N |
Verification
| Is a Document Verification Plan Available? | Yes, document only plan |
| Test Methodology | Directed Testing |
| Assertions | N |
| Coverage Metrics Collected | None |
| Timing Verification Performed? | Y |
| Timing Verification Report Available | N |
| Simulators Supported | Mentor ModelSIM |
Hardware Validation
| Validated on FPGA | Y |
| Hardware Validation Platform Used | ZC702 |
| Industry Standard Compliance Testing Passed | N |