logiCVC-ML Compact Multilayer Video Controller

  • Part Number: logiCVC-ML
  • Vendor: Xylon d.o.o.
  • Partner Tier: Premier

Product Description

The logiCVC-ML IP core is an advanced display graphics controller that enables an easy video and graphics integration into embedded systems with the AMD SoC, MPSoC and FPGA devices. It can be used as a standalone graphics IP core, or as a part of larger graphics systems along with other Xylon logicBRICKS IP cores. The logiCVC-ML is a real plug-and-play IP core, prepared for AMD Vivado Design Suite, and designers familiar with these tools can immediately start designing. The IP's size and features can be easily adjusted through IP drag and drop tools GUI interface. The logiCVC-ML comes ready-to-use and with the rich set of deliverables including SW driver and documentation. Currently Xylon offers software drivers for use with Linux®, Android(TM) and Microsoft® Windows® Embedded Compact operating systems. Free Xylon reference design for popular Zynq 7000 SoC based development kits enable quick and risk-free evaluation.

Key Features and Benefits

  • Supported output formats: Parallel RGB, Parallel YUV, PAL/NTSC, LVDS, Camera link, DVI
  • Configurable AMBA AXI4, AXI4-Lite and AXI4-Stream interfaces
  • Pixel, Layer, or Color Lookup Table (CLUT) alpha blending
  • Configurable layer's size, position and offset
  • Supports up to 5 layers
  • Up to 8192x8192 display resolutions (including 4K2K@60)
  • Supports LCD TFT and CRT displays
  • Software drivers for Linux, Android and Microsoft Windows Embedded Compact
  • Free reference designs: logiREF-ZGPU-ZC702, logiREF-ZGPU-ZC706, logiREF-ZGPU-ZED

Featured Documents

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
Zynq-UP-MPSoC Family XCZU9EG -2 Vivado ML 2021.1 Y 0 908 8 0 0 0 333
VERSAL_AI_CORE Family XCVC1902 -1 Vivado 2019.1 Y 0 1235 7 10 0 0 200
KINTEX-7 Family XC7K355T -2 Vivado 2018.2 Y 285 477 1 0 0 0 200
ARTIX-7 Family XC7A100T -2 Vivado 2018.2 Y 283 443 1 0 0 0 130
Zynq-7000 Family XC7Z020 -1 Vivado 2016.2 Y 281 489 1 0 0 0 220
Spartan 6 Family XC6SLX25 -3 Vivado 2014.4 Y 411 808 2 0 0 0 206
VIRTEX6LXT Family XC6VLX75T -1 Vivado 2014.4 Y 394 681 767 0 0 0 200

IP Quality Metrics

General Information

This Data was Current On Oct 23, 2023
Current IP Revision Number 5.5.2
Date Current Revision was Released Jan 20, 2022
Release Date of First Version Apr 09, 2010

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 80
Can References be Made Available? Y


IP Formats Available for Purchase Bitstream, Netlist, Source Code
Source Code Format(s) VHDL
High-Level Model Included? N
Integration Testbench Provided Y
Integration Test Bench Format(s) VHDL
Code Coverage Report Provided? N
Functional Coverage Report Provided? N
UCFs Provided? UCF
Commercial Evaluation Board Available? Y
FPGA Used on Board Zynq UltraScale+ MPSoC
Software Drivers Provided? Y
Driver OS Support Linux, WEC7, Android


Code Optimized for Xilinx? Y
Standard FPGA Optimization Techniques Inference, Instantiation
Synthesis Software Tools Supported/Version Xilinx XST
Static Timing Analysis Performed? Y
AXI Interfaces AXI4, AXI4-Lite
IP-XACT Metadata Included? N


Is a Document Verification Plan Available? Yes, document only plan
Test Methodology Directed Testing
Assertions Y
Coverage Metrics Collected None
Timing Verification Performed? Y
Timing Verification Report Available N
Simulators Supported Mentor ModelSIM

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used ZCU102, ZC702