Product Description
Our JPEG core is an 12-bit JPEG encoder for still image and video compression applications. This core is extremely high speed performance, capable of compressing 140MPixels/sec for 4-2-0 images in the AMD Zynq 7000 or Spartan 6 FPGA. The A2e core is also one of the smallest on the market, requiring less than 500 slices in a Spartan 6 FPGA. This core also supports true mono mode.
Key Features and Benefits
- Extremely high speed performance
- Small size
Device Implementation Matrix
Device utilization metrics for example implementations of this core. Contact provider for more information.
| Family | Device | Speed Grade | Tool Version | HW Validated? | Slice | LUT | BRAM | DSP48 | CMT | GTx | FMAX (Mhz) |
|---|---|---|---|---|---|---|---|---|---|---|---|
| Zynq-7000 Family | XC7Z020 | -1 | Vivado ML 2022.1 | Y | 1088 | 1400 | 9 | 3 | 0 | 0 | 0 |
IP Quality Metrics
General Information
| This Data was Current On | Nov 27, 2023 |
| Current IP Revision Number | 2.0100 |
| Date Current Revision was Released | Jan 01, 2014 |
| Release Date of First Version | Jan 01, 2013 |
Production Use by Xilinx Customers
| Number of Successful Xilinx Customer Production Projects | 4 |
| Can References be Made Available? | Y |
Deliverables
| IP Formats Available for Purchase | Netlist, Source Code |
| Source Code Format(s) | VHDL |
| High-Level Model Included? | Y |
| Model Formats | C |
| Integration Testbench Provided | Y |
| Integration Test Bench Format(s) | Verilog |
| Code Coverage Report Provided? | N |
| Functional Coverage Report Provided? | N |
| UCFs Provided? | N |
| Commercial Evaluation Board Available? | N |
| Software Drivers Provided? | N |
Implementation
| Code Optimized for Xilinx? | N |
| Synthesis Software Tools Supported/Version | Xilinx XST |
| Static Timing Analysis Performed? | Y |
| IP-XACT Metadata Included? | N |
Verification
| Is a Document Verification Plan Available? | Executable and documented plan |
| Test Methodology | Constrained random testing |
| Assertions | N |
| Coverage Metrics Collected | Functional |
| Timing Verification Performed? | Y |
| Timing Verification Report Available | Y |
| Simulators Supported | Xilinx lSim |
Hardware Validation
| Validated on FPGA | Y |
| Hardware Validation Platform Used | Zynq |
| Industry Standard Compliance Testing Passed | N/A |
| Specific Compliance Test | Yes |
| Test Date | Jan 06, 2013 |
| Are Test Results Available? | N |