25G/10G/1G TCP/IP + MAC Ethernet IP Cores

  • Part Number: nxTCP Standard Edition
  • Vendor: Enyx SA
  • Alliance Member
  • Application Partner

Product Description

The world’s most reliable and mature full hardware TCP/IP and MAC IP Cores: Bring the best-in-class network connectivity to your hardware design with Enyx rock-solid and acclaimed Ethernet IP Cores. Minimize time-to-market with our full RTL implementation and support. Stay always at the forefront of technology with our frequent updates with the latest improvements and optimizations.


Key Features and Benefits

  • 40G/25G/10G/1G Ethernet connectivity. Maximum bandwidth delivered with low latency.
  • Full RTL Layers 2, 3 and 4, which include Enyx proprietary full-hardware TCP/IP, ARP, ICMP and MAC implementations.
  • Easy to use standardized AXI-4 interfaces.
  • Multiple instances per FPGA and multiple logical interfaces per instance, each of them with a unique IPv4, MAC address, VLAN ID, Gateway and Mask.
  • Up to 32768 TCP simultaneous sessions per instance, each of them configurable dynamically in server or client mode.

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
VIRTEX-UP Family XCVU9P -2 Vivado 2017.3 Y 0 37000 79 0 0 0 156

IP Quality Metrics

General Information

This Data was Current On Nov 12, 2020
Current IP Revision Number 2.4.0
Date Current Revision was Released May 01, 2019
Release Date of First Version Jan 01, 2011

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 0
Can References be Made Available? Y

Deliverables

IP Formats Available for Purchase Source Code
Source Code Format(s) VHDL, Verilog
High-Level Model Included? N
Integration Testbench Provided Y
Integration Test Bench Format(s) Verilog
Code Coverage Report Provided? N
Functional Coverage Report Provided? N
UCFs Provided? XDC
Commercial Evaluation Board Available? Y
FPGA Used on Board Virtex UltraScale+
Software Drivers Provided? N/A

Implementation

Code Optimized for Xilinx? Y
Standard FPGA Optimization Techniques Inference, Instantiation, UltraFast Design Methodology
Custom FPGA Optimization Techniques None
Synthesis Software Tools Supported/Version Vivado Synthesis / 2017.3
Static Timing Analysis Performed? Y
AXI Interfaces AXI4-Stream, AXI4-Lite
IP-XACT Metadata Included? N

Verification

Is a Document Verification Plan Available? Yes, document only plan
Test Methodology Both
Assertions Y
Coverage Metrics Collected Code
Timing Verification Performed? Y
Timing Verification Report Available Y
Simulators Supported Other; Mentor ModelSIM

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used VU9P
Industry Standard Compliance Testing Passed N
Are Test Results Available? N