NVMe IP core

Product Description

NVMe IP core is standalone NVMe Host Controller with built-in optimized PCIe Bridge and Internal Memory Buffer, designed to handle NVMe Protocol without need CPU/OS and External DDR memory. It’s recommended for the application which requires high performance, high storage capacity, very compact system size and easily to support multiple NVMe SSDs.This IP core license includes the reference design for Xilinx FPGA boards. It helps you to reduce development time and cost.


Key Features and Benefits

  • Implement application layer to access NVMe PCIe SSD without CPU and external memory (DDR)
  • Simple user control I/F and FIFO interface for data port
  • Direct connect to Integrated Block for PCI Express from Xilinx by using 128-bit bus interface
  • Include 256 Kbyte RAM to be data buffer
  • Support 6 commands, i.e. IDENTIFY, WRITE, READ, Shutdown, SMART, and Flush
  • exFAT & FAT32 file system management without CPU usage (Option)
  • Support PCIe Switch (Customize support, please ask us)
  • Reference design with AB17-M2FMC or AB18-PCIeX16 adapter board available on Xilinx FPGA boards

Featured Documents

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
VIRTEX-UP Family XCVU9P -2 Vivado 2017.4 Y 1718 2954 66 0 0 0 400
Zynq-UP-MPSoC Family XCZU7EV -2 Vivado 2017.4 Y 1868 2955 66 0 0 0 400
VIRTEX-7X Family XC7VX690T -2 Vivado 2017.4 Y 1591 3204 66 0 0 0 300
VIRTEX-7X Family XC7VX485T -2 Vivado 2017.4 Y 1638 3203 66 0 0 0 300
KINTEX-7 Family XC7K325T -2 Vivado 2017.4 Y 1574 3204 66 0 0 0 300
ARTIX-7 Family XC7A200T -2 Vivado 2017.4 Y 1500 3089 66 0 0 0 225
Zynq-7000 Family XC7Z045 -2 Vivado 2017.4 Y 1532 3201 66 0 0 0 300
KINTEX-U Family XCKU040 -2 Vivado 2017.4 Y 1684 2951 66 0 0 0 400

IP Quality Metrics

General Information

This Data was Current On May 05, 2020
Current IP Revision Number 4.2
Date Current Revision was Released Dec 20, 2018
Release Date of First Version Jun 01, 2016

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 22
Can References be Made Available? Y

Deliverables

IP Formats Available for Purchase Netlist
Source Code Format(s) VHDL
High-Level Model Included? N
Integration Testbench Provided N
Code Coverage Report Provided? N
Functional Coverage Report Provided? N
UCFs Provided? SDF
Commercial Evaluation Board Available? Y
FPGA Used on Board Zynq UltraScale+ MPSoC
Software Drivers Provided? N

Implementation

Code Optimized for Xilinx? N
Custom FPGA Optimization Techniques None
Synthesis Software Tools Supported/Version Xilinx XST
Static Timing Analysis Performed? N
AXI Interfaces AXI4
IP-XACT Metadata Included? N

Verification

Is a Document Verification Plan Available? No
Test Methodology Directed Testing
Assertions N
Coverage Metrics Collected Functional
Timing Verification Performed? N
Timing Verification Report Available N
Simulators Supported Xilinx lSim

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used KCU105, VC707, ZCU102, ZCU106, VCU118
Industry Standard Compliance Testing Passed N
Are Test Results Available? N