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NVMe IP core

Product Description

NVMe IP core is standalone NVMe Host Controller with built-in optimized PCIe Bridge and Internal Memory Buffer, designed to handle NVMe Protocol without need CPU/OS and External DDR memory. It’s recommended for the application which requires high performance, high storage capacity, very compact system size and easily to support multiple NVMe SSDs.This IP core license includes the reference design for Xilinx FPGA boards. It helps you to reduce development time and cost.


Key Features and Benefits

  • Simple user control I/F and FIFO interface for data port
  • Automatic 512/4K sector LBA support
  • Implement application layer to access NVMe PCIe SSD without CPU and external memory (DDR)
  • Direct connect to Integraged Block for PCI Express from Xilinx by using 128-bit bus interface
  • Support 6 commands, i.e. IDENTIFY, WRITE, READ, Shutdown, SMART, and Flush
  • Reference design with AB16-PCIeXOVR or AB17M2FMC adapter board is available on Xilinx FPGA boards

Featured Documents

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
Zynq-UP-MPSoC Family XCZU7EV -2 Vivado 2017.4 Y 0 2955 66 0 0 0 400
VIRTEX-7X Family XC7VX485T -2 Vivado 2014.4 Y 576 1486 0 0 0 0 125
KINTEX-U Family XCKU040 -2 Vivado 2015.4 Y 341 1465 0 0 0 0 250

IP Quality Metrics

General Information

This Data was Current On Feb 20, 2019
Current IP Revision Number 4.2
Date Current Revision was Released Dec 20, 2018
Release Date of First Version Jun 01, 2016

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 17
Can References be Made Available? Y

Deliverables

IP Formats Available for Purchase Netlist
Source Code Format(s) VHDL
High-Level Model Included? N
Integration Testbench Provided N
Code Coverage Report Provided? N
Functional Coverage Report Provided? N
UCFs Provided? SDF
Commercial Evaluation Board Available? Y
FPGA Used on Board Zynq UltraScale+ MPSoC
Software Drivers Provided? N

Implementation

Code Optimized for Xilinx? N
Custom FPGA Optimization Techniques None
Synthesis Software Tools Supported/Version Xilinx XST
Static Timing Analysis Performed? N
AXI Interfaces AXI4
IP-XACT Metadata Included? N

Verification

Is a Document Verification Plan Available? No
Test Methodology Directed Testing
Assertions N
Coverage Metrics Collected Functional
Timing Verification Performed? N
Timing Verification Report Available N
Simulators Supported Xilinx lSim

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used KCU105, VC707, ZCU102, ZCU106, VCU118
Industry Standard Compliance Testing Passed N
Are Test Results Available? N
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