NVMe IP core is NVMe Host Controller IP with no CPU and OS required. Enabling NVMe SSD interface for a wide range of AMD FPGA devices. Ideal for simple and high performance NVMe SSD interface without CPU and external memory. Allow to build multi-channel RAID systems with very high performance and lowest possible FPGA resources consumption. This IP core license includes the reference design for AMD FPGA boards. It helps you to reduce development time and cost.
Device utilization metrics for example implementations of this core. Contact provider for more information.
Family | Device | Speed Grade | Tool Version | HW Validated? | Slice | LUT | BRAM | DSP48 | CMT | GTx | FMAX (Mhz) |
---|---|---|---|---|---|---|---|---|---|---|---|
VIRTEX-UP Family | XCVU9P | -2 | Vivado 2019.1 | Y | 859 | 2954 | 66 | 0 | 0 | 0 | 400 |
Zynq-UP-MPSoC Family | XCZU7EV | -2 | Vivado 2019.1 | Y | 934 | 2955 | 66 | 0 | 0 | 0 | 400 |
VIRTEX-7X Family | XC7VX690T | -2 | Vivado 2019.1 | Y | 1591 | 3204 | 66 | 0 | 0 | 0 | 300 |
VIRTEX-7X Family | XC7VX485T | -2 | Vivado 2019.1 | Y | 1638 | 3203 | 66 | 0 | 0 | 0 | 300 |
KINTEX-7 Family | XC7K325T | -2 | Vivado 2019.1 | Y | 1574 | 3204 | 66 | 0 | 0 | 0 | 300 |
ARTIX-7 Family | XC7A200T | -2 | Vivado 2019.1 | Y | 1500 | 3089 | 66 | 0 | 0 | 0 | 225 |
Zynq-7000 Family | XC7Z045 | -2 | Vivado 2019.1 | Y | 1532 | 3201 | 66 | 0 | 0 | 0 | 300 |
KINTEX-U Family | XCKU040 | -2 | Vivado 2019.1 | Y | 842 | 2951 | 66 | 0 | 0 | 0 | 400 |
This Data was Current On | Mar 26, 2024 |
Current IP Revision Number | 4.4 |
Date Current Revision was Released | Sep 07, 2023 |
Release Date of First Version | Jun 01, 2016 |
Number of Successful Xilinx Customer Production Projects | 56 |
Can References be Made Available? | Y |
IP Formats Available for Purchase | Netlist |
Source Code Format(s) | VHDL |
High-Level Model Included? | N |
Integration Testbench Provided | N |
Code Coverage Report Provided? | N |
Functional Coverage Report Provided? | N |
UCFs Provided? | SDF |
Commercial Evaluation Board Available? | Y |
FPGA Used on Board | Zynq UltraScale+ MPSoC |
Software Drivers Provided? | N |
Driver OS Support | NA |
Code Optimized for Xilinx? | N |
Custom FPGA Optimization Techniques | None |
Synthesis Software Tools Supported/Version | Xilinx XST |
Static Timing Analysis Performed? | N |
AXI Interfaces | AXI4 |
IP-XACT Metadata Included? | N |
Is a Document Verification Plan Available? | No |
Test Methodology | Directed Testing |
Assertions | N |
Coverage Metrics Collected | Functional |
Timing Verification Performed? | N |
Timing Verification Report Available | N |
Simulators Supported | Xilinx lSim |
Validated on FPGA | Y |
Hardware Validation Platform Used | KCU105, VC707, ZCU102, ZCU106, VCU118, KCU116 |
Industry Standard Compliance Testing Passed | N |
Are Test Results Available? | N |