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SD Card / eMMC Host IP Core

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Product Description

The SD 3.0/SDIO 3.0/eMMC 5.1 Host IP from Arasan Chip Systems is a highly integrated host controller IP solution that supports three key memory card I/O technologies: SD 3.0 SDIO 3.0 eMMC 5.1 The SD 3.0 / eMMC 5.1 Host IP handles all of the timing and interface protocol requirements to access these media as well as processing the commands in hardware thereby scaling in both performance and access speeds. The IP supports connection to a single slot and performs multi-block writes and erases that lower access overhead. In addition, a host can utilize this IP to boot directly from an attached eMMC memory, thereby simplifying system initialization during power up. The host interface is based on a standard 32-bit AHB bus which is used to transfer data and configure the SD 3.0 / eMMC5.1 Host IP. eMMC 5.1 is backward compatible to the previous versions. Tools used Vivado 2022.1 Arasan's IP is also available to license for ASIC applications. Arasan offers a licensing scheme to go from FPGA to ASIC at reduced license fees.

Key Features and Benefits

  • Compliant with eMMC Specification Version 5.1
  • AMBA AXI Specification Version 3.00 (Standard)
  • AMBA AHB Specification Version 2.00 (Optional)
  • OCP specification Version 2.2 (Optional)
  • Host clock rate variable between 0 and 200 MHz
  • Supports one of the following System/Host Interfaces: AHB, AXI or OCP
  • Data transfer using PIO mode on the Host Bus Slave interface, using DMA mode on the Host Bus Master interface. Here the Host Bus is AHB or AXI or OCP Interface
  • Supports eMMC5.1 Security Protocol Commands
  • Supports 32-bit and 64-bit system bus
  • Configurable FIFO size to support different block sizes
  • Supports Interrupts and wake up functionality
  • Supports Internal Clock divider for various card operational modes
  • HS400 high speed interface timing mode of up to 400 MB/s data rate
  • Field firmware update
  • eMMC device health report
  • eMMC production state awareness
  • Secure removal types
  • Backward compatible to 1-bit, 4-bit and 8-bit modes
  • Supports Primary & alternate boot modes
  • Supports Packed commands, Data Tags, Discard & Sanitize features
  • Supports 4KB block support
  • Supports Tuning for HS200 mode
  • Cyclic Redundancy Check CRC7 for command and CRC16 for data integrity
  • Supports MMC Plus and MMC Mobile
  • Password protection of Cards
  • SD Host Controller Spec v3.0* (SDXC)
  • SDIO Spec v3.0
  • SD Memory Spec v3.01
  • eSD Memory Spec v2.1

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
VIRTEX-UP Family XCVU13P -2 Vivado ML 2022.1 Y 0 10916 0 0 0 0 200

IP Quality Metrics

General Information

This Data was Current On Oct 23, 2023
Current IP Revision Number 1P12
Date Current Revision was Released Mar 11, 2016
Release Date of First Version Oct 12, 2014

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 10
Can References be Made Available? Y

Deliverables

IP Formats Available for Purchase Source Code
Source Code Format(s) Verilog
High-Level Model Included? Y
Model Formats Other
Integration Testbench Provided Y
Integration Test Bench Format(s) OVM System Verilog
Code Coverage Report Provided? Y
Functional Coverage Report Provided? Y
UCFs Provided? XDC
Commercial Evaluation Board Available? N
FPGA Used on Board Virtex UltraScale+
Software Drivers Provided? Y
Driver OS Support Yes

Implementation

Code Optimized for Xilinx? Y
Standard FPGA Optimization Techniques UltraFast Design Methodology
Custom FPGA Optimization Techniques Vivado
Synthesis Software Tools Supported/Version Xilinx XST
Static Timing Analysis Performed? Y
AXI Interfaces AXI4-Lite
IP-XACT Metadata Included? Y

Verification

Is a Document Verification Plan Available? Yes, document only plan
Test Methodology Both
Assertions Y
Coverage Metrics Collected Code
Timing Verification Performed? Y
Timing Verification Report Available Y
Simulators Supported Cadence NC-Sim

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used Arasan board
Industry Standard Compliance Testing Passed N
Are Test Results Available? N