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ACE-NIC

  • Part Number: ACE-NIC
  • Vendor: Ethernity Networks
  • Ecosystem Program Tier: Member

Product Description

ACE-NIC is an open flow enabled software acceleration NIC, operated on top of COTS servers. ACE-NIC accelerates performance by 50 times, dramatically reducing end-to-end latency associated with NFV platforms. Applications include vSwitch offloading (OVS offload), SD-WAN and vCPE, vEPC (full data plane for vSGW and vPGW), vRouter, vBRAS/vBNG, vPE Router, Edge data appliances and vFW, network overlay/underlay offloading, data centre gateways (DC-GW), monitoring, and SLA.


Key Features and Benefits

  • 40G non-blocking throughput
  • OpenFlow enabled
  • Protocol interworking, including support for 3GPP gateway, VxLAN, NVGRE, PB, QinQ, IP and others
  • 256K entries search filter
  • Per-flow rules, including header manipulation, filtering, switching, time stamping and programmable header compression
  • Load balancing at VM granularity
  • Integrated packet generator and analyser to support wire speed OAM/CFM functions
  • Programmable fragmentation and reassembly
  • Per-frame nanosecond accuracy time stamping
  • Wire speed NAPT
  • Hierarchical queuing, scheduling and shaping
  • L2/L3/L4 switch
  • IPSec Tunnel option available per project

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
KINTEX-7 Family XC7K410T -2 Vivado 2017.2 Y 52000 196877 369 2 7 10 200

IP Quality Metrics

General Information

This Data was Current On May 11, 2018
Current IP Revision Number 1.3.4
Date Current Revision was Released Apr 15, 2018
Release Date of First Version Jan 18, 2018

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 2
Can References be Made Available? N

Deliverables

IP Formats Available for Purchase Bitstream, Netlist
Source Code Format(s) Verilog
High-Level Model Included? Y
Model Formats C++
Integration Testbench Provided Y
Integration Test Bench Format(s) C/C++
Code Coverage Report Provided? N
Functional Coverage Report Provided? Y
UCFs Provided? N
Commercial Evaluation Board Available? Y
FPGA Used on Board Kintex-7
Software Drivers Provided? Y
Driver OS Support All

Implementation

Code Optimized for Xilinx? Y
Standard FPGA Optimization Techniques Instantiation
Custom FPGA Optimization Techniques None
Synthesis Software Tools Supported/Version Synplicity Synplify
Static Timing Analysis Performed? Y
AXI Interfaces AXI4, AXI4-Lite
IP-XACT Metadata Included? Y

Verification

Is a Document Verification Plan Available? Executable and documented plan
Test Methodology Both
Assertions Y
Coverage Metrics Collected Functional
Timing Verification Performed? Y
Timing Verification Report Available Y
Simulators Supported Mentor Questa

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used ENET Evaluation Board
Industry Standard Compliance Testing Passed Y
Specific Compliance Test MEF and others
Test Date Apr 02, 2018
Are Test Results Available? Y
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