Product Description
The Adeas ST 2110 Video over IP core enables standards based media transport over IP for providing individual packetization of video, audio and metadata. The ST 2110 Core Suite supports the following: ST 2110-10 - System Timing, ST 2110-20 - Uncompressed Video Stream, ST 2110-21 - Traffic Shaping, ST 2110-22 compressed video, ST 2110-30&31 - Audio Stream, ST 2110-40 - Ancillary Data (Metadata), NMOS IS-04 - Discovery and Registration, IS-05 - Connection Management, IS-07 Event & Tally, IS-08 - audio muxing, IS-09 System Parameters. For interfacing with ST 2022 streams a ST 2022-6/8 IP core is available as well as several other "helper" IP-cores to build a system. Our field proven ST 2059 companion core is designed to work seamlessly along side the ST 2110 core to offer a complete ecosystem for professional media over IP.
Key Features and Benefits
- Fully Integrated ST 2059 Core (Optional)
- NMOS Software Core
- Optimized ST 2110 Hardware Core
- HD, UHD and 8K Video Support
Device Implementation Matrix
Device utilization metrics for example implementations of this core. Contact provider for more information.
| Family | Device | Speed Grade | Tool Version | HW Validated? | Slice | LUT | BRAM | DSP48 | CMT | GTx | FMAX (Mhz) |
|---|---|---|---|---|---|---|---|---|---|---|---|
| Zynq-UP-MPSoC Family | XCZU7EV | -2 | Vivado ML 2021.2 | Y | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| Kintex-UP Family | XCKU3P | -1 | Vivado ML 2021.2 | Y | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| KINTEX-U Family | XCKU040 | -2 | Vivado 2018.3 | Y | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
IP Quality Metrics
General Information
| This Data was Current On | Oct 24, 2023 |
| Current IP Revision Number | v3.5 (reference design) |
| Date Current Revision was Released | Feb 02, 2022 |
| Release Date of First Version | Jan 16, 2018 |
Production Use by Xilinx Customers
| Number of Successful Xilinx Customer Production Projects | 1 |
| Can References be Made Available? | Y |
Deliverables
| IP Formats Available for Purchase | Source Code |
| Source Code Format(s) | VHDL |
| High-Level Model Included? | N |
| Integration Testbench Provided | N |
| Code Coverage Report Provided? | N |
| Functional Coverage Report Provided? | N |
| UCFs Provided? | XDC |
| Commercial Evaluation Board Available? | Y |
| FPGA Used on Board | Kintex UltraScale+ |
| Software Drivers Provided? | Y |
| Driver OS Support | Petalinux |
Implementation
| Code Optimized for Xilinx? | Y |
| Standard FPGA Optimization Techniques | Other Optimization Techniques |
| Custom FPGA Optimization Techniques | None |
| Synthesis Software Tools Supported/Version | Vivado Synthesis / 2021.1 |
| Static Timing Analysis Performed? | Y |
| AXI Interfaces | AXI4-Lite, AXI4-Stream |
| IP-XACT Metadata Included? | Y |
Verification
| Is a Document Verification Plan Available? | No |
| Test Methodology | Directed Testing |
| Assertions | Y |
| Coverage Metrics Collected | None |
| Timing Verification Performed? | Y |
| Timing Verification Report Available | Y |
| Simulators Supported | Xilinx lSim |
Hardware Validation
| Validated on FPGA | Y |
| Hardware Validation Platform Used | KCU-116, ZCU-106 |
| Industry Standard Compliance Testing Passed | Y |
| Specific Compliance Test | 2110 interops, JTNM tested events |
| Test Date | Mar 30, 2020 |
| Are Test Results Available? | Y |