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ENET3850Z/99

Product Description

ENET3850Z/99 is a flow processor for G.fast solutions, supporting Carrier Ethernet switch, BBF WT-301, G.999.1 channelized Ethernet, and EFM bonding. ENET3850Z/99 is implemented on Xilinx’s Zynq 7015 and integrates dual-core ARM Cortex-9 CPUs and programmable logic. ENET3850Z/99 is specially optimized for the FTTdp G.fast market, supporting 16 modems


Key Features and Benefits

  • Flexible interface support that can be customized to any port/interface configuration
  • Family of G.fast solutions from 6Gbps with 2.5G NI
  • External buffering
  • Integrated ARM dual-core Cortex 9 powerful CPU
  • Enhanced flexibility, configurability, and programmability, including field upgradability
  • Carrier Ethernet switching
  • EFM bonding to support up to 2 groups
  • MEF-compliant advanced Traffic Manager, including support for flow policing and shaping per virtual port/G.fast modem
  • QoS, including WFQ, WRR, WRED and Strict Priority
  • Supports 8/16 G.fast modems
  • Programmable protocol interworking
  • Extended buffer space through DDR3
  • RPF: less than 3W at 5Gbps (ideal for reverse power feeding)

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
Zynq-7000 Family XC7Z015 -2 Vivado 2016.2 Y 39468 38860 93 2 1 3 125

IP Quality Metrics

General Information

This Data was Current On May 11, 2018
Current IP Revision Number 80.0.01.4
Date Current Revision was Released Oct 31, 2016
Release Date of First Version Feb 08, 2016

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 2
Can References be Made Available? N

Deliverables

IP Formats Available for Purchase Netlist
Source Code Format(s) Verilog
High-Level Model Included? Y
Model Formats C++
Integration Testbench Provided N
Integration Test Bench Format(s) C/C++
Code Coverage Report Provided? N
Functional Coverage Report Provided? Y
UCFs Provided? N
Commercial Evaluation Board Available? Y
FPGA Used on Board Zynq-7000
Software Drivers Provided? Y
Driver OS Support all

Implementation

Code Optimized for Xilinx? Y
Standard FPGA Optimization Techniques Instantiation
Custom FPGA Optimization Techniques None
Synthesis Software Tools Supported/Version Vivado Synthesis
Static Timing Analysis Performed? Y
AXI Interfaces AXI4-Lite, AXI4
IP-XACT Metadata Included? Y

Verification

Is a Document Verification Plan Available? Executable and documented plan
Test Methodology Both
Assertions Y
Coverage Metrics Collected Functional
Timing Verification Performed? Y
Timing Verification Report Available N
Simulators Supported Mentor Questa

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used ENET EVB
Industry Standard Compliance Testing Passed Y
Specific Compliance Test MEF and others
Test Date May 12, 2016
Are Test Results Available? Y
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