Product Description

The ENET4840Z/99 is a Flow Processor for Broadband Access solutions. It supports Carrier Ethernet switch, OAM/CFM, BBF WT-301, G.999.1 channelized Ethernet, and EFM bonding. The ENET4840Z/99 is implemented on Xilinx’s Zynq family and integrates dual-core ARM Cortex 9 CPUs and programmable logic. The ENET4840Z/99 is specially optimized as a scale-up solution for the FTTdp market, as it is capable of supporting up to 48 modems, through G.999.1 over 10G interfaces

Key Features and Benefits

  • Flexible interface support that can be customized to any port/interface configuration
  • Supporting up to 48 G.fast modems
  • QoS including WFQ, WRR, WRED, and Strict Priority
  • Overlay network technologies, including VxLAN and NVGRE
  • MEF-compliant advanced Traffic Manager, including support for flow policing and shaping per virtual port/G.fast modem
  • Programmable protocol interworking
  • EFM bonding to support up to 24 groups
  • ACL L2/L3/L4
  • OAM/CFM – 802.1ag/ Y.17131
  • Carrier Ethernet switching
  • External buffering
  • Enhanced flexibility, configurability, and programmability, including field upgradability
  • Integrated powerful dual-core ARM Cortex 9 CPU
  • G.fast solution up to 40Gbps with 2.5G/10G network interfaces

Featured Documents

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
Zynq-7000 Family XC7Z035 -2 Vivado 2017.2 Y 0 118178 343 204 3 5 200

IP Quality Metrics

General Information

This Data was Current On May 21, 2020
Current IP Revision Number 2.1.0
Date Current Revision was Released Feb 08, 2018
Release Date of First Version Feb 08, 2017

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 2
Can References be Made Available? N


IP Formats Available for Purchase Netlist
Source Code Format(s) Verilog
High-Level Model Included? N
Integration Testbench Provided Y
Integration Test Bench Format(s) C/C++
Code Coverage Report Provided? Y
Functional Coverage Report Provided? Y
UCFs Provided? N
Commercial Evaluation Board Available? Y
FPGA Used on Board Zynq-7000
Software Drivers Provided? Y
Driver OS Support All


Code Optimized for Xilinx? Y
Standard FPGA Optimization Techniques Instantiation
Custom FPGA Optimization Techniques None
Synthesis Software Tools Supported/Version Synplicity Synplify
Static Timing Analysis Performed? Y
AXI Interfaces AXI4-Lite, AXI4
IP-XACT Metadata Included? Y


Is a Document Verification Plan Available? Executable and documented plan
Test Methodology Both
Assertions Y
Coverage Metrics Collected Functional
Timing Verification Performed? Y
Timing Verification Report Available Y
Simulators Supported Mentor Questa

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used ENET EVB
Industry Standard Compliance Testing Passed Y
Specific Compliance Test MEF and others
Test Date May 17, 2017
Are Test Results Available? Y