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  • Part Number: EVB4845Z
  • Vendor: Ethernity Networks
  • Alliance Program Tier: Member

Product Description

ENET4845Z EVB is the reference design kit for the ENET48xx 40G Carrier Ethernet switch SoC on FPGA. It offers an entire Carrier Ethernet switch and traffic manager integrated on Xilinx’s Zynq 7045 FPGA, with 12 x 1G user ports, 2 x 10G SFP+ interfaces, and 40G of switching capacity.

Key Features and Benefits

  • Hierarchical traffic management, scheduling, metering and shaping
  • Header compression/decompression (special request)
  • TR101, TR-156, TR-301
  • Wire speed NAT/NAPT
  • Y.1731, RFC2544, 802.1ag, OAM, MPLS OAM, BFD, Y.1564
  • LAG (L2, L3, L4 distribution)
  • L2 VPN (special request)
  • Various types of editing and packet duplication/multicast
  • Five-level packet header & payload manipulation and marking: MPLS/PBB/PB (PBB and MPLS special request)
  • Switch, router, and load balancing functions
  • Search engine with 256K entries (16 tables)
  • IPSec tunnel with additional VxLAN, NVGRE (special request) overlays

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
Zynq-7000 Family XC7Z045 -3 Vivado 2016.4 Y 169319 163721 466 11 8 4 175

IP Quality Metrics

General Information

This Data was Current On Apr 02, 2019
Current IP Revision Number
Date Current Revision was Released Nov 30, 2017
Release Date of First Version Sep 30, 2016

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 3
Can References be Made Available? N


IP Formats Available for Purchase Netlist
Source Code Format(s) Verilog
High-Level Model Included? Y
Model Formats C++
Integration Testbench Provided Y
Integration Test Bench Format(s) C/C++
Code Coverage Report Provided? Y
Functional Coverage Report Provided? Y
UCFs Provided? N
Commercial Evaluation Board Available? Y
FPGA Used on Board Zynq-7000
Software Drivers Provided? Y
Driver OS Support All


Code Optimized for Xilinx? Y
Standard FPGA Optimization Techniques Instantiation
Custom FPGA Optimization Techniques None
Synthesis Software Tools Supported/Version Synplicity Synplify
Static Timing Analysis Performed? Y
AXI Interfaces AXI4-Lite, AXI4
IP-XACT Metadata Included? Y


Is a Document Verification Plan Available? Executable and documented plan
Test Methodology Both
Assertions Y
Coverage Metrics Collected Functional
Timing Verification Performed? Y
Timing Verification Report Available N
Simulators Supported Mentor Questa

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used ENET EVB
Industry Standard Compliance Testing Passed Y
Specific Compliance Test MEF and others
Test Date Oct 31, 2016
Are Test Results Available? Y
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