SLVS-EC RX IP Core

  • Part Number: SLVS-EC RX IP Core
  • Vendor: FRAMOS
  • Member Partner

Product Description

The SLVS-EC RX IP Core reduces overhead and complexity implementing a SLVS-EC based SONY imager. As an on-chip function block connecting the customer’s FPGA logic with the image sensor’s data stream, this IP Core receives the interface data, manages the byte-to-pixel conversion for various lane configurations and then prepares a highly-efficient processing workflow run on the FPGA. The FRAMOS software supports SLVS-EC v1.2 and v2.0 with 1, 2, 4, 8 lanes which are configurable by the user and delivers pixels formats of 8 to 14-bit of raw data. By de-risking the sensor implementation, this core significantly reduces the development efforts and accelerates time to market.

The IP Core is available for the following devices:

  • Xilinx Artix-7™
  • Xilinx Kintex-7™
  • Xilinx Zynq-7000™ SoC
  • Xilinx Kintex UltraScale™
  • Xilinx Kintex UltraScale+™
  • Xilinx Zynq UltraScale+™ MPSoC

    A complete Evaluation Kit is available separately. Compatibility for additional devices available on request.


    Key Features and Benefits

    • Byte-to-pixel conversion for SLVS-EC
    • De-risk integration, reduce time to market
    • Reference implementation for evaluation and guidance
    • Flexible Lane Support in one IP Core
    • Support for common RAW bit-depths
    • Dynamic mode change support
    • AXI4 communication and control

    Featured Documents

  • Device Implementation Matrix

    Device utilization metrics for example implementations of this core. Contact provider for more information.

    Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
    Zynq-UP-MPSoC Family XCZU9EG -2 Vivado 2020.2 Y 543 2514 0 0 0 0 300
    Kintex-UP Family XCKU5P -2 Vivado 2020.2 Y 561 2516 0 0 0 0 300
    KINTEX-7 Family XC7K325T -2 Vivado 2020.2 Y 930 2468 0 0 0 0 270
    ARTIX-7 Family XC7A200T -2 Vivado 2020.2 Y 985 2529 0 0 0 0 270
    Zynq-7000 Family XC7Z045 -2 Vivado 2020.2 Y 919 2470 0 0 0 0 300
    KINTEX-U Family XCKU040 -2 Vivado 2020.2 Y 559 2517 0 0 0 0 300

    IP Quality Metrics

    General Information

    This Data was Current On Oct 19, 2021
    Current IP Revision Number 1.1.1
    Date Current Revision was Released Oct 19, 2018
    Release Date of First Version May 14, 2018

    Production Use by Xilinx Customers

    Number of Successful Xilinx Customer Production Projects 10
    Can References be Made Available? Y

    Deliverables

    IP Formats Available for Purchase Source Code, Netlist
    Source Code Format(s) VHDL
    High-Level Model Included? N
    Integration Testbench Provided Y
    Integration Test Bench Format(s) VHDL
    Code Coverage Report Provided? N
    Functional Coverage Report Provided? N
    UCFs Provided? XDC
    Commercial Evaluation Board Available? N
    Software Drivers Provided? N

    Implementation

    Code Optimized for Xilinx? N
    Custom FPGA Optimization Techniques None
    Synthesis Software Tools Supported/Version Vivado Synthesis / 2016.4
    Static Timing Analysis Performed? Y
    AXI Interfaces AXI4-Lite
    IP-XACT Metadata Included? Y

    Verification

    Is a Document Verification Plan Available? No
    Test Methodology None
    Assertions N
    Coverage Metrics Collected None
    Timing Verification Performed? N
    Timing Verification Report Available N
    Simulators Supported Mentor ModelSIM / PE 10.5c

    Hardware Validation

    Validated on FPGA Y
    Hardware Validation Platform Used KCU116, KCU105, AC701, KC705, ZC706, ZCU102
    Industry Standard Compliance Testing Passed N
    Are Test Results Available? N