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AVB/Automotive Ethernet Switch IP Core

  • Part Number: S-3133
  • Vendor: SoC-e
  • Certified Partner

Product Description

AVB/Automotive Ethernet Switch (AVBES) IP Core implements an Ethernet switch which supports all AVB conforming standards. It can be implemented optimally depending on the application, from a simple 2-ports end-point to a complex multiport switch.

The current release of AVBES IP supports 802.1AS for timing and synchronization, 802.1Qav allowing credit-based shaper traffic and strict priority traffic. In order to manage network resources, AVBES supports also 802.1Qat, Stream Reservation Protocol.

AVBES IP can be optimally implemented on Xilinx SoC devices. As an example, targeted devices are Xilinx Zynq-7000 SoC and Zynq Ultrascale+ MPSoC. These powerful platforms offer combined hardware and software processing capabilities and they ensure upgradeability of the solution thanks to their reconfigurable nature.

AVBES IP can be evaluated using the AVBES Kit and can be combined with SoC-e Multiport FMC Board to offer a complete solution to automotive market.

Key Features and Benefits

  • Broadcast/Multicast Storm Protection
  • Configurable 3 to 32 Ethernet ports
  • Different data rate (10/100/1000 Mbps) for each port
  • Dynamic MAC Table with automatic MAC addresses learning and aging (up to 4096 entries)
  • Full-Duplex Ethernet 10/100/1000
  • IEEE 802.1AS for Time Synchronization Layer
  • IEEE 802.1Qat for Stream Reservation Protocol (SRP) - Network resources management
  • IEEE 802.1Qav for Forwarding and Queuing for Time-Sensitive Streams (FQTSS) - Credit Based Shaper: Configurable bandwidth reservation for each traffic class
  • Jumbo Frame Management
  • MDIO, UART, AXI4-lite or CoE (Configuration-over-ethernet) management interfaces
  • MII/RMII/GMII/RGMII/SGMII/QSGMII/USXGMII interfaces for attaching to an external Physical Layer device (PHY)
  • Port-based VLAN support
  • Static MAC Table (up to 4096 entries)
  • Full-duplex 2.5/5/10 Gbps Ethernet Uplink Interfaces
  • Per-Port Rate limiting (Broadcast, Multicast and Unicast traffic)

Featured Documents

Device Implementation Matrix

Device utilization metrics for example implementations of this core. Contact provider for more information.

Family Device Speed Grade Tool Version HW Validated? Slice LUT BRAM DSP48 CMT GTx FMAX (Mhz)
Zynq-7000 Family XC7Z020 -1 Vivado 2018.3 6072 16418 72 0 0 0 125

IP Quality Metrics

General Information

This Data was Current On Oct 11, 2021
Current IP Revision Number 18.11
Date Current Revision was Released Oct 31, 2018
Release Date of First Version Oct 29, 2018

Production Use by Xilinx Customers

Number of Successful Xilinx Customer Production Projects 1
Can References be Made Available? N


IP Formats Available for Purchase Netlist, Source Code
Source Code Format(s) VHDL
High-Level Model Included? N
Integration Testbench Provided N
Code Coverage Report Provided? N
Functional Coverage Report Provided? N
UCFs Provided? XDC
Commercial Evaluation Board Available? Y
FPGA Used on Board Zynq-7000
Software Drivers Provided? Y
Driver OS Support Yes (Linux)


Code Optimized for Xilinx? N
Custom FPGA Optimization Techniques None
Synthesis Software Tools Supported/Version Vivado Synthesis / 2015.4; Vivado Synthesis / 2017.2
Static Timing Analysis Performed? Y
AXI Interfaces AXI4-Stream, AXI4-Lite
IP-XACT Metadata Included? Y


Is a Document Verification Plan Available? No
Test Methodology Directed Testing
Assertions N
Coverage Metrics Collected Functional
Timing Verification Performed? Y
Timing Verification Report Available Y
Simulators Supported Xilinx lSim

Hardware Validation

Validated on FPGA Y
Hardware Validation Platform Used SMARTzynq/SMARTmpsoc
Industry Standard Compliance Testing Passed N
Are Test Results Available? N