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AXI HBICAP

Overview

Product Description

The Xilinx AXI High Bandwidth Internal Configuration Access Port (HBICAP) LogiCORE IP core for the AXI Interface enables an embedded microprocessor, such as the MicroBlaze processor, to read and write the FPGA configuration memory through the internal configuration access port (ICAPEn). This enables you to write software programs that modify the circuit structure and functionality during the operation of the circuit.


Key Features and Benefits

  • Supports ICAPEn both in internal and external modes
  • Supports STARTUPEn both in internal and external modes
  • AXI4-Lite interface for control path
  • Memory mapped AXI4 slave interface for read and write data paths with maximum bursts of256 beats per transaction
  • Optional AXI4-Stream master interface for read datapath with unlimited burst per transaction
  • Supports write and read transfers up to 230 bytes in size
  • Cut-through write path with no separate control on initiating write transfers
  • Lock bit option to hold the control on ICAP when ICAP is in sharing mode with other blocks
  • Indicates the read FIFO full condition through an output that can be used to gate the ICAPclock
  • Interrupts for write and read paths based on FIFO conditions
  • Soft reset, FIFO only reset options
  • Status register to indicate the configuration Done and EoS
  • Supports ICAP abort operation
  • Supports independent read FIFO and write FIFO disable options

Note: The ICAPE2 primitive is applicable for 7 series devices. The ICAPE3 primitive is applicable forUltraScale™ and UltraScale+™ devices.


Resource Utilization

Support

Documentation

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