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AXI Spartan-6 DDRX Memory Controller

Product Description

The Advanced eXtensible Interface (AXI) Spartan-6 FPGA DDRx Memory Controller core provides a high-performance multi-ported AXI4 slave front-end connection to LPDDR SDRAM / DDR / DDR2 / DDR3 external memory. This core uses the Memory Control Block (MCB) primitive and adapts the MCB native interface to use the AXI4 slave interface. This provides full functionality of all the features present on the Spartan-6 MCB core.

Key Features & Benefits

  • Supports Read-only and Write-only modes
  • Global reset, all ports reset synchronously
  • Supports AXI INCR/WRAP only; no FIXED mode support
  • Supports a mode to guarantee write coherency between ports
  • Does not reorder transactions
  • Round-Robin Read/Write arbitration
  • Up to six AXI4 slave compliant memory interfaces

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Tools and Device Support

Device Family Support:

Design Tools Support:

  • Bundled With: Embedded Development Kit
  • License: Xilinx End User License Agreement

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