Important Notice:
This IP Core has been discontinued. Effective Date: 10/27/2021
It is not recommended for new designs. The core will be removed from IP catalog as of 2022.1.
Product Description
The 3GPP LTE Channel Decoder provides a high-performance, optimized decode function for the Uplink Shared Channel (UL-SCH), as defined in 3GPP. Core Generator options allow the user to generate underlying transport block and channel quality information decode chains, supporting applications such as relay nodes. The 3GPP LTE Channel Decoder is a component in Xilinx LTE Baseband Targeted Design Platform.
Key Features and Benefits
- Uplink Shared Channel decoder for 3GPP TS 36.212 v9.3.0
- Transport Block Decoder and Channel Quality Information Decoder sub-components can be Generated as stand-alone cores
- TDD/FDD compliant
- Support for on or off chip codeword buffering
- Integrated descrambling
- Integrated LLR calculation
- Fully decoupled decoding chains
- Fully optimized for speed and area
- Fully synchronous design using a single clock
- Bit Accurate C model
- Customer demonstration test bench
Resource Utilization
Support
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