The Xilinx LogiCORE™ DSP48 Macro provides an easy-to-use interface that abstracts the DSP48 slice and simplifies its dynamic operation by enabling the specification of multiple operations via a set of user defined arithmetic expressions. The specified operations are enumerated and can be selected by the user via a single port on the generated core.
The DSP48 Macro provides a simplified interface to the DSP48 slice by the abstraction of all opmode, subtract, alumode and inmode controls to a single SEL port. Further, all CE and RST controls are grouped to a single CE and SCLR port respectively. This abstraction enhances portability of HDL between device families. The DSP48 Macro supports a square latency model where additional register stages are added so all input to output paths have the same latency. The Macro supports 3 latency modes (automatic, tiered and expert). Automatic and tiered are square latency models, the difference being that auto gives fully pipelined whereas tiered allows finer control. This can be useful when utilizing the DSP48 slice as a processing engine. Alternatively, all additional pipeline stages can be removed to use the minimum of resources. The DSP48 Macro is recommended for applications that do not require the full versatility of control of the DSP48 slices and for applications where portability is a high priority.
Finally, the DSP48 Macro supports all the common instructions of the DSP48 slice while achieving maximum performance.