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Xilinx supports Full System Hardware Evaluation. The evaluation license key for this core will enable you to parameterize, generate and instantiate this IP in your design. It will also allow you to perform functional and timing simulation, generate a bitstream, and download and configure your design in hardware. The resulting IP will be fully functional in the FPGA for certain period of time, after which it will cease to function. To restore the evaluation core's operation in your design, simply reconfigure the FPGA with the bitstream.


Please refer to the Requirements link on the product page for this core for information on Software Requirements.

License Terms

Please note that the terms of the Core Evaluation License Agreement apply toward your evaluation of this core.

Registration Instructions

  • Access to this evaluation core is available to approved customers
  • Customers interested in evaluating this core must register for access to the Evaluation Lounge. Your evaluation request will be reviewed by Xilinx IP Marketing
  • All required fields in the web registration form must be filled in accurately. The email address associated with your Xilinx.com account must also be a valid company email address in order for your registration to be approved.
  • Xilinx reserves the right to decline evaluation requests for these cores

Accessing Evaluation Files

To perform a Full System Hardware Evaluation:

  1. Make sure you have satisfied the Software Requirements for this core.
  2. Register to request access to the Evaluation Lounge (see Quick Links box). Xilinx IP Marketing will review your request.
  3. Upon receiving approval, log into the Evaluation Member Lounge to access the data sheet and Bit Accurate C-Model.
  4. You will also receive instructions by email from Xilinx Customer Service on how to generate an Evaluation License key on the Xilinx Product Licensing site.

Note: The evaluation core will cease to function in a programmed FPGA device after a period of time.

General Instructions

You can customize the IP for use in your design by specifying values for the various parameters associated with the IP core using the following steps:

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