The Xilinx® LogiCORE™ 32G Fibre Channel (32GFC) RS-FEC IP core implements the Reed-Solomon Forward Error Correction (RS-FEC) sublayer as described in the INCITS Fibre Channel Framing and Signaling T11/15-253v2 specification.
Key Features and Benefits
Low latency design
Configuration and status bus
Example reference design demonstrating of RS-FEC and GT Wizard cores
ECC RAM option
Supports all features required for CPRI v7.0 operation