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LDPC Encoder / Decoder

Overview

Product Description

Forward Error Correction (FEC) codes such as Low Density Parity Check (LDPC) codes provide a means to control errors in data transmissions over unreliable or noisy communication channels. The LDPC Encoder/Decoder core provides an optimized block for encoding and soft-decision decoding of these codes. Custom and standardized LDPC codes are supported through the ability to specify the parity check matrix through an AXI4-Lite bus.


Key Features and Benefits

  • Optimized for 5G Wireless (backhaul and baseband) and DOCSIS 3.1 applications
  • Highly configurable codes
    • A range of Quasi-Cyclic codes can be configured over an AXI4-Lite interface
    • Code parameter memory can be shared across up to 128 codes
    • Codes can be selected on a block-by-block basis
  • Normalized min-sum decoding algorithm
    • Normalization factor programmable (from 0.0625 to 1 in steps of 0.0625) for layers
  • Number of iterations between 1 and 63
    • Specified for each codeword
  • Early termination
    • Specified for each codeword to be none, one, or both of the following:
      • Parity check passes
      • No change in hard information or parity bits since last iteration
  • When configured as a decoder, soft or hard outputs
    • Specified for each codeword to include information and optional parity
  • In- or out-of-order execution of blocks, with user specified ID field to identify blocks

Resource Utilization


Support

Documentation
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