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  3. NVMe Target Controller (NVMeTC)

NVMe Target Controller (NVMeTC)

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Overview

Product Description

The AMD NVMe Target Controller IP allows for the implementation of an NVMe device inside the FPGA. The IP works in tandem with the AMD QDMA Subsystem for PCI Express and exposes an NVMe 1.3 spec compliant device view to the host.

Key Features and Benefits

The IP manages the following functions:

  1. Exposes and emulates the NVMe controller registers as defined in the NVMe 1.3 specification.
  2. Manages the Submission Queue (SQ)/Completion Queue (CQ) doorbells from the host.
  3. Arbitrates across available SQs and programs the QDMA to fetch the required Submission Queue entries (SQEs).

 

  1. Parses the SQEs and programs the QDMA to fetch the SGLs/PRP list if applicable.
  2. Programs the QDMA for data transfer between host and FPGA (for reads or writes) based on instruction from the application/user logic.

IP Performance and Resource Utilization Data

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