Hardware Evaluation Time Out Period * : ~ 8 hrs
|LogiCORE™||Version||AXI Support||Software Support||Supported Device Families|
|O-RAN Radio Interface||v2.0||AXI4-Stream||Vivado® 2021.1||Versal™ ACAP
Zynq UltraScale+ MPSoC
Zynq UltraScale+ RFSoC
* A Hardware Evaluation license for any of the IP cores above will enable you to parameterize, generate and instantiate these cores in your design. You will also be able to perform functional and timing simulation and generate a bitstream that you can use to download and configure your design in hardware.
The IP cores in this table will be fully functional in the programmed device for certain amount of time. After this time, the IP will "time out" (cease to function) and you will need to download and configure the FPGA again.