ThunderBus IP


Product Description

The ThunderBus IP core provides a high data throughput solution for off chip connectivity over Xilinx Gigabit Transceiver (GT’s). Xilinx’s ThunderBus IP-Core provides multilane GT connectivity between different devices.

Key Features and Benefits

  • Full AXIS/AXIMM protocol support per lane
  • Up to 52 bit sideband signal per lane
  • Selectable number of lanes per quad from 1 to 16
  • Adjustable Line Rate (in Gbps)
    • For all supported devices: 0.5 to 13.75 (only up to 12.5 for -1 parts)
    • For supported devices with GTY: 0.5 to 28.21 (only up to 25.785 for -1 parts)
  • Adjustable Ref Clock selection
    • Clock selections based from chosen Line Rate
  • Supports Transceiver type selection
    • GTHE3, GTHE4, GTYE3, GTYE4
  • Selectable GT Locations
    • Overwritable locations with XDC constraints
  • Enable BERT for Debugging live system


The configuration is in the custom page properties
The configuration is in the custom page properties

Featured Documents

Default Default Title Document Type Date