We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

Xilinx HMC Controller IP Core Evaluation

Xilinx provides two ways to evaluate this LogiCORE™ IP core: Simulation Only, and Full System Hardware Evaluation.

  • Simulation Only Evaluation allows you to customize the core through the Vivado® IDE.
  • A Full System Hardware Evaluation version of the core allows you to do everything you can do with the Fully Licensed IP core, including configure, place and route, simulate, estimate timing and program a Xilinx FPGA device.


Please refer to the Requirements link on the product page for this core for information on Software Requirements.

License Terms

Please note that the terms of the Core Evaluation License Agreement apply toward your evaluation of this core. 

Accessing Evaluation Files

  1. Make sure you have satisfied the Software Requirements for this core.
  2. Follow the Installation Instructions in the Master IP Release Note Guide to install the required ISE® software and IP Update.
  3. Follow the general instructions below to access and evaluate the core.
  1. Make sure you have satisfied the Software Requirements for this core.
  2. Generate a Full System Hardware Evaluation License Key (see Quick Links box).
    • The license will be generated and emailed to you automatically. Install the license as directed by the email instructions.
  3. Follow the general instructions below to load the IP Catalog customization GUI for this core and generate the core.
  4. For some cores, an Example Design is written to your project directory by the IP Catalog when you generate the core. If an example design is provided, instructions will be documented in a Product Guide document.
  5. To perform an in-depth evaluation in hardware in your own design:
    • Instantiate the core in your own design, place and route the design using Vivado, then generate a bitstream and use it to program an appropriate FPGA device.
    Note: The evaluation core will cease to function in a programmed FPGA device after a period of time.

General Instructions

You can customize the IP for use in your design by specifying values for the various parameters associated with the IP core using the following steps:

Page Bookmarked