IBERT for 7 Series GTX Transceivers


Product Description

The customizable LogiCORE™ IP Integrated Bit Error Ratio Test (IBERT) core for 7 series FPGA GTX transceivers is designed for evaluating and monitoring the GTX transceivers. This core includes pattern generators and checkers that are implemented in FPGA logic, and access to ports and the dynamic reconfiguration port attributes of the GTX transceivers. Communication logic is also included to allow the design to be run time accessible through JTAG. This core can be used as a self-contained or open design, based on customer configuration, and as described in this document.

Key Features and Benefits

  • Provides a communication path between the Vivado® serial I/O analyzer software and the IBERT core
  • Provides a user-selectable number of 7 series FPGA GTX transceivers
  • Transceivers can be customized for the desired line rate, reference clock rate, reference clock source, and datapath width
  • Requires a system clock that can be sourced from a pin or one of the enabled GTX transceivers

Resource Utilization



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