The customizable LogiCORE™ IP Integrated Bit Error Ratio Tester (IBERT) core for UltraScale/UltraScale+ architecture GTH transceivers is designed for evaluating and monitoring the GTH transceivers. This core includes pattern generators and checkers that are implemented in FPGA logic, and access to ports and the dynamic reconfiguration port attributes of the GTH transceivers. Communication logic is also included to allow the design to be run time accessible through JTAG. This core can be used as a self-contained or open design, based on customer configuration.
Key Features and Benefits
- Provides a communication path between the Vivado® serial I/O analyzer feature and the IBERT core
- Provides a user-selectable number of UltraScale architecture GTH transceivers
- Transceivers can be customized for the desired line rate, reference clock rate, and reference clock source
- Requires a system clock that can be sourced from a pin or one of the enabled GTH transceivers