IBERT for UltraScale GTM Transceivers


Product Description

The Xilinx® LogiCORE™ IP Integrated Bit Error Ratio Tester (IBERT) core for UltraScale™ architecture GTM transceivers is designed for evaluating and monitoring the GTM transceivers. This core includes pattern generators and checkers that are implemented in the GTM transceivers, and access to ports and the dynamic reconfiguration port attributes of the GTM transceivers. Communication logic is also included to allow the design to be run-time accessible through JTAG. This core can be used as a self-contained or an open design based on your configuration, and as described in this document.

Key Features and Benefits

  • Provides a communication path to the Vivado® Serial I/O analyzer feature
  • Provides a user-selectable number of Virtex® UltraScale+™ architecture GTM transceivers
  • Transceivers can be customized for the desired line rate, reference clock rate, and reference clock source
  • Requires a system clock that can be sourced from a pin or one of the enabled GTM transceivers
  • Supports PAM4 and NRZ signal modulations
  • Forward error correction (FEC) mode with PAM4 signaling is supported



Featured Documents

Default Default Title Document Type Date