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Processor Local Bus (PLB) 4.6

Product Description

The Xilinx 128-bit Processor Local Bus (PLB) v4.6 provides bus infrastructure for connecting an optional number of PLB masters and slaves into an overall PLB system. It consists of a bus control unit, a watchdog timer, and separate address, write, and read data path units. It contains an optional DCR slave interface to provide access to its bus error status registers.

Key Features & Benefits

  • PLB arbitration support for up to 16 masters
    • Number of PLB masters is configurable via a design parameter
  • PLB address and data steering support for up to 16 masters
  • 128-bit, 64-bit, and 32-bit support for masters and slaves
  • PLB address pipelining
  • Three-cycle arbitration
  • Four levels of dynamic master request priority

Featured Documents

Tools and Device Support

Device Family Support:

Design Tools Support:

  • License: Xilinx End User License Agreement
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