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Phase Locked Loop (PLL) Module

Product Description

The Phase Locked Loop primitive in Virtex-5 FXT parts is used to generate multiple clocks with defined phase and frequency relationships to a given input clock. The Phase Locked Loop (PLL) module is a wrapper around the PLL_ADV primitive that allows the PLL to be used in the EDK tool suite.

Key Features & Benefits

  • Wrapper around the PLL_ADV primitive
  • Full support for use with EDK 9.1 and later versions
  • Configurable BUFG insertion
  • Configurable output delay adjustment for PPC block clock insertion delay compensation
  • Six output clocks with independently selectable frequencies

Tools and Device Support

Device Family Support:

xilinx-131x43
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