Virtex 5 Endpoint Block Plus Wrapper for PCI Express (PCIe)


Product Description

AMD provides the ability to configure the FPGA Built-in Endpoint Block for PCIe available in Virtex 5 FPGAs. In addition to configuring the block, the core also provides all of the supplemental logic required to deliver a complete Endpoint solution for PCIe. This AMD Endpoint Block Plus Wrapper for PCIe simplifies the design process and reduces time-to-market. Many easy-to-use features and optimal configuration for Endpoint applications are available at no additional cost. This solution can be used in communication, multimedia, server and mobile platforms and enables applications such as high-end medical imaging, graphics intensive video games, DVD quality streaming video on the desktop and 10 Gigabit Ethernet interface cards. This core combined with other AMD connectivity solutions helps customers preserve their investment in older technologies by allowing seamless bridging to other standard and proprietary interfaces. All registered ISE users can request a license file by clicking the “Get License” button on this page.

Key Features and Benefits

  • Compliant with the PCI Express Base Specification 1.1
  • Fully compliant with PCI Express transaction ordering rules
  • Supports maximum payload of 512 bytes
  • 1 Virtual Channel
  • Support lane width, x1, x4 and x8
  • Bandwidth scalability interconnect width
  • Pre-implemented optimal buffering for high bandwidth applications
  • LocalLink User Interface for easy bridging to other AMD IP
  • Supports removal of corrupted packets for error detection and recovery
  • Uses Virtex 5 GTP/GTX Transceivers
  • Design verified by an AMD proprietary testbench
  • Tested at PCI-SIG compliance workshop and included on PCI Express Integrators List


Device Family:

Related Products:


Featured Documents

Default Default Title Document Type Date