Virtex 6 Integrated Block for PCI Express (PCIe)


Product Description

AMD provides a Virtex™ 6 FPGA Endpoint solutions for PCI Express® (PCIe) to configure the Virtex 6 FPGA Integrated Block for PCIe FPGA and includes additional logic to create a complete solution for PCIe. This AMD Block Wrapper for PCIe simplifies the design process and reduces time-to-market. Many easy-to-use features and optimal configuration for Endpoint and Root Port applications are available at no additional cost. This solution can be used in communication, multimedia, server and mobile platforms and enables applications such as high-end medical imaging, graphics intensive video games, DVD quality streaming video on the desktop and 10 Gigabit Ethernet interface cards. This core combined with other AMD  connectivity solutions helps customers preserve their investment in older technologies by allowing seamless bridging to other standard and proprietary interfaces. All registered ISE users can request a license file by first registering for the wrapper (“Register”)

Recommended for:

  • High Performance and High Bandwidth applications
  • Compute and Data Co-processing Applications
  • Medical Imaging, High-Performance Computing & Communications Packet Processing


The AMD Integrated Block for PCIe is provided at no additional cost. Click the “Get License” link for instructions.

Key Features and Benefits

  • Compliant with the PCI Express Base Specification 2.0
  • Fully compliant with PCI Express transaction ordering rules
  • Supports maximum payload of 1024 bytes (for most configurations)
  • 1 Virtual Channel
  • Supported Lane width: x1, x2, x4 and x8
  • Bandwidth scalability interconnect width
  • Pre-implemented optimal buffering for high bandwidth applications
  • LocalLink User Interface for easy bridging to other AMD IP
  • Uses Virtex 6 GTX Transceivers
  • Design verified by a proprietary test bench


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