This specification defines the architecture and interface requirements for the External Peripheral Controller (EPC). The controller supports data transfers between the Processor Local Bus (PLB) and the external synchronous and/or asynchronous peripheral devices.
Key Features and Benefits
- Connects as a 32-bit slave on PLB V4.6 buses of 32-bit, 64-bit or 128-bit
- PLB interface with byte enable support
- Parameterized support of up to four external peripheral devices with each device configured with separate base address and high address range
- Supports both synchronous and asynchronous access modes of peripheral devices with the support for a separate clock domain for synchronous peripheral devices
- Supports both multiplexed and non-multiplexed address and data buses