UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

XPS General Purpose IO

Product Description

This document describes the specifications for the General Purpose Input/Output (GPIO) core for the Processor Local Bus (PLB). The XPS GPIO is a 32-bit peripheral that attaches to the PLB.

Key Features & Benefits

  • PLB interface is based on PLB v4.6 specification
  • Configurable as single or dual GPIO channel(s)
  • Number of GPIO bits configurable from 1 to 32 bits
  • Each GPIO bit can be dynamically programmed as input or output
  • Can be configured as inputs-only on a per channel basis to reduce resource utilization
  • Ports for both 3-state and non 3-state connections

Featured Documents

Tools and Device Support

Device Family Support:

Design Tools Support:

xilinx-131x43
  • Bundled With: Embedded Development Kit
  • License: Xilinx End User License Agreement

Featured Documents

Page Bookmarked