Product Description

XPS_LL_TEMAC Ethernet core provides a control interface to internal registers via a 32-bit Processor Local Bus (PLB) Version 4.6 as described in the IBM CoreConnect™ 128-Bit Processor Local Bus, Architectural Specification Version 4.6. This PLB slave interface supports single beat read and write data transfers (no burst transfers).

TEMAC is an acronym for Tri-Mode Ethernet Media Access Controller and is a reference to the three speed (10, 100, and 1000 Mb/S) capable Ethernet MAC function available in this core.

Key Features and Benefits

  • Independent 2K, 4K, 8K, 16K, or 32K Byte TX and RX data FIFOs for queueing frames
  • Filtering of "bad" receive frames
  • Support for several PHY interfaces
  • Media Independent Interface Management access to PHY registers
  • Full Duplex operation
  • Optional support for jumbo frames up to 9K Bytes
  • Optional TX and RX TCP/UDP partial checksum off load in hardware
  • Support for VLAN frames
  • Support for Pause frames for flow control
  • Auto PAD and FCS field stripping or pass through on receive
  • One or two full duplex Ethernet bus interfaces with a shared control interface and independent data and interrupt interfaces



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