Xilinx provides the Processing System IP Wrapper for the Zynq UltraScale+ MPSoC to accelerate your design and its configuration for your embedded products
The Processing System IP is the software interface around the Zynq® Ultrascale+™ MPSoC Processing System. The Zynq UltraScale MPSoC family consists of a system-on-chip (SoC) style integrated processing system (PS) and a Programmable Logic (PL) unit, providing an extensible and flexible SoC solution on a single die.
The Processing System IP Wrapper acts as a logic connection between the PS and the PL while assisting you to integrate custom and embedded IPs with the processing system using the Vivado® IP integrator.
Key Features and Benefits
- Enable/Disable I/O Peripherals (IOP)
- Enable/Disable AXI I/O ports (AIO)
- MIO Configuration
- Extended MULTIPLE USE I/Os (EMIO)
- DDR Configuration
- Security and Isolation Configuration
- Interconnect logic for Vivado IP - PS interface
- PL Clocks and Interrupts