Three scalar processor types are available in Versal ACAPs to support diverse application needs. The application processing unit is ideal for complex applications supported by an OS, and the real-time processing unit is ideal for applications needing low latency, determinism, and real-time control. A separate platform management controller manages system boot, security, and debug.
Programmable logic enables the development of custom computational blocks for ever-changing algorithms. The rearchitected logic in Versal ACAPs provides 4X greater density per CLB, reducing the need for costly global routing. Loaded with a wide variety of memory elements and tightly coupled with programmable I/O, the adaptable engines allow users to create powerful accelerators for any application.
AI Engines provide up to 5X higher compute density for vector-based algorithms. Optimized for real-time DSP and AI/ML computation, AI Engines provide deterministic performance.
Enhanced DSP engines provide support for new operations and data types, including single and half-precision floating point and complex 18x18 operations.
The Versal AI Core series combines PCIe® Gen4 compliance, CCIX support, high performance GPIO, and multirate Ethernet MACs supporting various ethernet configurations to maximize connectivity and flexibility. Additionally, Versal AI Core series devices feature rearchitected low latency 32.75Gb/s transceivers.
Each integrated DDR memory controller provides up to 34.1GB/s of bandwidth with DDR4 and LPDDR4 support, and is optimized for both linear and random traffic. In combination with the programmable Network on Chip, these integrated controllers eliminate the need for soft implementations in the programmable logic, saving development time and logic resources.
The programmable network on chip (NoC) provides an optimized multi-terabit interconnect between the different compute engines and integrated IP blocks present in the Versal ACAP architecture, simplifying timing closure and saving logic resources. The NoC compiler provides a streamlined programming experience while allowing users to manage latency and QoS, ensuring that critical data paths are prioritized.
Beamforming results in enormous signal processing requirements that need to be processed in real time. While adaptable engines are handling status control and data formatting, AI Engines and DSP Engines are processing fixed & floating point signal processing workloads for high performance parallel processing.
As convolutional neural networks continue to evolve, the challenge to keep up with increasing computational density requirements can only be addressed by the Versal AI Core series devices, which have AI Engines optimized to efficiently deliver computational density, both cost effectively and power efficiently.
Versal AI Core series devices enable video surveillance for Smart Cities, with AI Engines driving real-time license plate or facial recognition, DSP engines for video transcoding, and adaptable engines for video scaling, compression, and customization.
Versal AI Core series accelerates parallel beamforming and real-time image processing to create higher quality images and machine-based image analysis to enable physicians and radiologists to make faster and more accurate diagnoses.
Merging powerful vector-based DSP engines with AI engines in a small form factor enables advanced radars, such as active electronically scanned arrays. AI Core series devices provide terabits per second of antenna bandwidth in a single package.
Real-time DSP is used extensively in wireless communications test equipment. Versal AI Engine architecture is well-suited to handle all types of protocol implementations, including 5G from the digital front end to beamforming and baseband.
|Application Processing Unit||Dual-core Arm® Cortex®-A72, 48KB/32KB L1 Cache w/ parity & ECC; 1MB L2 Cache w/ ECC|
|Real-time Processing Unit||Dual-core Arm Cortex-R5F, 32KB/32KB L1 Cache, and 256KB TCM w/ECC|
|Memory||256KB On-Chip Memory w/ECC|
|Connectivity||Ethernet (x2); USB 2.0 (x1); UART (x2); SPI (x2); I2C (x2); CAN-FD (x2)|
|System Logic Cells (K)||540||797||1,051||1,586||1,968|
|NoC Master / NoC Slave Ports||10||14||18||28||28|
|DDR Memory Controllers||2||2||2||4||4|
|CCIX & PCIe® w/ DMA (CPM)||-||1 x Gen4x16,
|-||1 x Gen4x16,
|1 x Gen4x16,
|PCIe||1 x Gen4x8||4 x Gen4x8||1 x Gen4x8||4 x Gen4x8||4 x Gen4x8|
|Multirate Ethernet MAC||1||4||3||4||4|
The Xilinx Vitis™ unified software platform provides comprehensive tools, libraries that use hardware-acceleration technology from the cloud to edge. The platform provides an efficient, convenient, and unified software environment across device nodes. As a proud member of the open source community, the Vitis unified software platform is entirely free and open source.
Be the first to experience the Versal ACAP architecture, built from the ground-up to be natively software programmable. Through a host of tools, software, libraries, IP, middleware, and frameworks, ACAPs enable dynamically customizable accelerated computing solutions through industry-standard design flows. The Versal AI Core series VCK190 evaluation kit has everything you need to jump-start your design on Versal ACAPs.