Versal AI Edge Series

Scalar Engines deliver power-efficient embedded compute with the safety and security required in real-time systems. The dual-core Arm® Cortex®-A72 application processor is ideal for running Linux-class applications, while the dual-core Arm Cortex-R5F real-time processor runs safety-critical code for the highest levels of functional safety (ASIL and SIL). The platform management controller (PMC) is based on a triple-redundant processor and manages device operation, including platform boot, advanced power and thermal management, security, safety, and reliability across the platform.

At the heart of the Versal architecture’s flexibility is its Adaptable Engines, enabling the integration of any sensor, connectivity to any interface, and the flexibility to handle any workload. Capable of both parallelism and determinism, Adaptable Engines can implement and adapt sensor fusion algorithms, accelerate pre- and post-data processing across the pipeline, implement deterministic networking and motor control for real-time response, isolate safety-critical functions for fail-safe operation, and allow for hardware redundancies and fault resilience.

Consisting of both AI Engines and DSP Engines, Intelligent Engines support a breadth of workloads common in edge applications including AI inference, image processing, and motion control. AI Engines are a breakthrough architecture based on a scalable array of vector processors and distributed memory, delivering breakthrough AI performance/watt. DSP Engines are based on the proven slice architecture in previous-generation Zynq™ adaptive SoCs, now with integrated floating-point support, and are ideal for wireless and image signal processing, data analytics, motion control, and more.

Versal ACAPs were built from the ground up to meet the most stringent safety requirements in industrial and automotive applications, including ISO 26262 and IEC 61508 for safety, and IEC 62443 for security. The Versal architecture is partitioned with safety features in each domain, as well as global resources to monitor and eliminate common cause failures. New security features over previous-generation adaptive SoCs improve protection against cloning, IP theft, and cyber-attacks, including higher bandwidth AES & SHA encryption/decryption, glitch detection, and more.

The accelerator RAM features 4MB of on-chip memory. The memory block is accessible to all compute engines and helps eliminate the need to go to external memory for critical compute functions such as AI inference. This enhances the already flexible memory hierarchy of the Versal architecture and improves AI performance/watt. The accelerator RAM is also ideal for holding safety-critical code that exceeds the capacity of the real-time processor’s OCM, improving the ability to meet ASIL-C and ASIL-D requirements.

Versal ACAP’s programmable I/O allows connection to any sensor or interface, as well as the ability to scale for future interface requirements. Designers can configure the same I/O for either sensors, memory, or network connectivity, and budget device pins as needed. Different I/O types provide a wide range of speeds and voltages for both legacy and next generation standards, e.g., 3.2Gb/s DDR for server-class memory interfacing, 4.2Gb/s LPDDR4x for highest memory bandwidth per pin, and native MIPI support to handle up to 8-megapixel sensors and beyond—critical to Level-2 ADAS and above.