Versal HBM Series

Hyper Integration of Fast Memory, Secure Data, and Adaptive Compute

Product Advantages

The Versal™ HBM series features heterogeneous integration of fast memory, secure connectivity, and adaptive compute to eliminate processing and memory bottlenecks for memory-bound, compute-intensive workloads such as machine learning, database acceleration, next-generation firewalls, and advanced network testers. It is built from the ground up to adapt to continually evolving algorithms, protocols, and data rates.

With the integration of HBM2e DRAM, the Versal HBM series provides 8X more bandwidth1 at 63% lower power than DDR5. Built on a production-proven Versal Premium ACAP foundation,  the Versal HBM series integrates an extensive set of networked, multi-terabit, power-optimized connectivity cores and 112G PAM4 transceivers to adapt to emerging network protocols and modules. While doubling the transceiver speed, the Versal HBM series secures every layer of the network infrastructure with built-in encryption engines. With the programmable network on chip (NoC), up to 2.2Tb/s of on-chip connectivity alleviates routing congestion between all engines. In addition, the Versal HBM series offers twice the logic density of the previous generation HBM solution to maximize performance for constantly evolving algorithms and protocols.

Versal HBM chip diagram

1: Based on a typical system implementation of four DDR5-6400 components

Key Features

Integrated HBM

Integrated HBM2e

Integration of HBM2e technology delivers up to 820GB/s memory bandwidth and 32GB capacity to minimize power, area, and latency for compute-intensive applications. Compared to commodity memory solutions (DDR5), the Versal HBM ACAP enables 8X more bandwidth at 63% lower power by placing stacked memory immediately adjacent to the compute fabric. Integrated HBM is globally accessible from anywhere on the device by the programmable NoC. With an integrated memory controller and enhanced hardened switch function, any memory location is accessible from any port.

Scalable Serial Bandwidth

Scalable Serial Bandwidth

Consisting of 58G/112Gb/s PAM4 and 32Gb/s NRZ transceivers, the Versal HBM series has very scalable transceivers that deliver up to 5.6Tb/s of serial I/O bandwidth. The 112G PAM4 transceivers allow the industry to roll out 800G and single-lane 100G capable infrastructure now. For 400G ramp and deployment, 58G PAM4 transceivers enable the latest generation interfaces for maximum bandwidth density. For mainstream power-optimized 100G interfaces, 32Gb/s NRZ transceivers are ideal.

Power-Optimized Networked, IP

Power-Optimized, Networked IP

High-performance connectivity is fundamental to next-generation networks and cloud infrastructure. The Versal HBM series delivers unprecedented integration of power-optimized hard IP, the equivalent logic density of 14 Virtex® UltraScale+™ FPGAs. The Versal HBM ACAP’s mix of high-speed Ethernet, Interlaken, and PCIe® Gen5 with DMA delivers multi-terabit connectivity with flexibility for a range of protocols and data rates. Line-rate High- Speed Crypto Engines enable network traffic to be fully secured.

 

Adaptable Engines

Adaptable Engines

At the heart of the Versal architecture's flexibility are its Adaptable Engines, enabling the development of custom computational blocks for differentiation, future-proofing, and the ability to adapt with ever-changing algorithms and protocols. Loaded with a wide variety of on-chip memory elements and tightly coupled with programmable I/O, the Adaptable Engines provide massive parallel processing and customization capability, critical for many compute-intensive workloads with large data sets.

Intelligent Engines

Intelligent Engines

The DSP Engines provide support for a variety of operations and data types, including single and half-precision floating-point and complex 18x18 operations. As enhancements of the previous generation technology, the DSP Engines are backwards compatible to UltraScale+ FPGA and SoC designs. Users can either leverage their existing libraries or update their designs for the maximum compute performance.

Scalar Engines

Scalar Engines

Three scalar processor types are available for diverse application needs. The application processing unit is ideal for complex applications supported by an OS, and the real-time processing unit is ideal for latency-sensitive applications. A separate platform management controller manages system boot, security, power management, and debug.


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Applications

Alleviating Processing and Memory Bottlenecks

Machine Learning Acceleration

Machine Learning Acceleration

Artificial intelligence and machine learning (AI/ML) evolve rapidly; complex algorithms need to process massive amounts of data, requiring enormous memory bandwidth. In the traditional compute architecture, when multiple CPU cores work simultaneously, the system stalls as data cannot move fast enough from external memory and eventually reaches the limit. In contrast, the Versal™ HBM series provides both massive parallel processing capability via Adaptable Engines and Intelligent Engines and enormous memory bandwidth via integrated HBM. As a result, the Versal HBM series enables accurate and faster data insights for many AI/ML processes such as Cosine Similarity and Louvain Modularity. With an extensive set of Vitis™ unified software platform's performance-optimized libraries, the Versal HBM ACAP based solution can deliver higher AI/ML performance and efficiency for fast-evolving AI for data centers and the cloud.


Compute Pre-Processing and Buffering

Pre-processing data is critical to achieve the best results from fixed-function compute devices. The size of datasets for real-world ML models can easily surpass the terabytes. Hence, the target accelerator needs large-scale pre-data processing frameworks to process these datasets efficiently. With the Adaptable Engines and 820GB/s of HBM bandwidth, the Versal HBM series removes unwanted data, transforms selected data, and augments data to create powerful predictive inputs for the target accelerator. Equipped with high-speed 112G PAM4 transceivers, the Versal HBM series maximizes throughput and system performance with low latency.

Compute Pre-Processing and Buffering

Next-Generation Firewall

Next-Generation Firewall

Network operators desire uninterrupted, intelligent management, and robust network availability to secure data and avoid attacks on enterprise networks.
The Versal HBM series enables unmatched scalability for implementing multi-layer network security from physical and data link layers to VPNs to transport layer security levels with 10s of millions of concurrent sessions with customized policies and controls. Moreover, multiple 400G integrated High-Speed Crypto (HSC) Engines allow the system to maintain line-rate throughput and low latency without compromising the performance. With 32G HBM, next-generation firewalls can manage multiple look-up tables without accessing external memories to buffer and reorder network flows. 112G PAM4 transceivers enable support for the latest optical standards and protocols for scalability to higher throughput needed by next-generation firewalls. Adaptable Engines enable ML algorithms to modernize security architecture against emerging threats.


Application Performance Test Equipment

As data center, cloud, and AI networks have begun gearing up for 800G optical connectivity, many data center networking and cloud providers need to leverage bleeding-edge test equipment to ensure interoperability and robust network infrastructure for compute-intensive applications.
112G PAM4 transceivers in Versal HBM devices are one of the most important building blocks for data center networking and cloud providers to build networks that can adapt to emerging protocols and interoperability with optics. Dedicated channelized multirate Ethernet cores feature individually accessible HSC, MAC, PCS, and FEC blocks alongside 32G HBM, and programmable NoC to implement the most complex test logic for massive traffic buffering, efficient data movement, intelligent data-flow control, tracking, and reporting for L4-L7 test equipment.

Application Performance Test Equipment
Product Table

Versal HBM Series Product Table

Memory Features

  VH1522 VH1542 VH1582 VH1742 VH1782
HBM DRAM (GB) 8 16 32 16 32
Total Block RAM (Mb) 89 89 89 132 132
UltraRAM (Mb) 366 366 366 541 541
Total PL Memory (Mb) 509 509 509 752 752

Intelligent Engines Features

  VH1522 VH1542 VH1582 VH1742 VH1782
DSP Engines 7,392 7,392 7,392 10,848 10,848

Adaptable Engines Features

  VH1522 VH1542 VH1582 VH1742 VH1782
System Logic Cells (K) 3,837 3,837 3,837 5,631 5,631
LUTs (M) 1.75 1.75 1.75 2.57 2.57

Scalar Engine Features

  VH1522 VH1542 VH1582 VH1742 VH1782
Application Processing Unit Dual-core Arm® Cortex®-A72, 48KB/32KB L1 Cache w/ parity & ECC; 1MB L2 Cache w/ ECC
Real-Time Processing Unit Dual-core Arm Cortex-R5F, 32KB/32KB L1 Cache, and 256KB TCM w/ECC
Memory 256KB On-Chip Memory w/ECC
Connectivity Ethernet (x2); UART (x2); CAN-FD (x2); USB 2.0 (x1); SPI (x2); I2C (x2)

Platform Features

  VH1522 VH1542 VH1582 VH1742 VH1782
32.75Gb/s Transceivers 68 68 68 68 68
GTM 56G (112G) 20 (10) 20 (10) 20 (10) 60 (30) 60 (30)
CCIX & PCIe® w/ DMA (CPM) 2 2 2 2 2
PCIe 8 8 8 8 8
High-speed Crypto Engines 2 2 2 3 3
100G Multirate Ethernet MAC 4 4 4 6 6
600G Ethernet MAC 1 1 1 3 3
600G Interlaken 0 0 0 1 1
Documentation

Documentation


Versal Design Guidance and Documentation

Xilinx provides a breadth of documentation, resources, and methodologies to accelerate your development on the Versal architecture. If you’re not sure where to begin with Versal ACAPs, the Design Flow Assistant is an interactive guide to help you create a development strategy, while the Design Process Hubs are a visual and streamlined reference to all Versal documentation by design process.


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Get Started

Early Access Program

The Versal™ HBM series is currently in Early Access. Contact your local Xilinx sales representative to apply for the Early Access program or visit the Contact Sales page. Leverage the resources below to learn more about design tools and design methodologies for the Versal ACAP architecture. 


Integrated Software and Hardware Platform for All Developers

With an inherently software programmable silicon infrastructure, the Versal ACAP is designed from the ground up to be software-centric. The enhanced Xilinx® Vivado® Design Suite introduces a new system design methodology and development environments such as traffic analyzer, NoC compiler, data flow modeling, and more. A high-speed, unified, cohesive debug environment accelerates debug and trace across Scalar, Adaptable, and Intelligent Engines.
Download Vivado Design Suite >

The Xilinx Vitis™ unified software platform provides comprehensive core development kits, libraries that use hardware-acceleration technology. The platform provides an efficient, convenient, and unified software environment from the cloud to the edge. As a proud member of the opensource community, the Vitis unified software platform is free and offers an extensive set of open-source, performance-optimized libraries that offer out-of-the-box acceleration with minimal to zero code changes to your existing applications.
Download Vitis Unified Software Platform >

Versal Prime Series

Start Developing using the Versal Premium VPK120 Evaluation Kit

Designers who are targeting a Versal HBM device can get started now with the Versal Premium VPK120 Evaluation Kit. Versal HBM devices are based on the same architecture as the Versal Premium series, with common architectural blocks such as Scalar Engines (Arm® processing subsystem), Adaptable Engines (programmable logic), DSP Engines, programmable network on chip (NoC), and connectivity blocks including PCIe®, 400G High-Speed Crypto Engines, 600G Ethernet MAC, 100G multirate Ethernet MAC, 600G Interlaken cores,  and DDR4 controller. The evaluation kit has everything you need to jump-start your design, including the ability to perform system testing, evaluate key interfaces, and adopt the ACAP design methodology.

Versal Premium VPK120 Evaluation Kit is currently in Early Access. Contact your local Xilinx sales representative to apply for the Early Access program or visit the Contact Sales page.


Training Courses

Xilinx training and learning resources provide the practical skills and fundamental knowledge you need to be fully productive in your next development project.

Getting Started with the Xilinx Versal™ ACAP Platform
Designing with the Versal ACAP: Power and Board Design
Designing with the Versal ACAP: Architecture and Methodology
Designing with the Versal ACAP: Programmable Network on Chip


Versal Design Guidance and Documentation

Xilinx provides a breadth of documentation, resources, and methodologies to accelerate your development on the Versal architecture. If you’re not sure where to begin with Versal ACAPs, the Design Flow Assistant is an interactive guide to help you create a development strategy, while the Design Process Hubs are a visual and streamlined reference to all Versal documentation by design process.

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