Versal Premium Series
The Highest Bandwidth and Compute Density
On an Adaptable Platform
From Network to Cloud
Breakthrough Integration of Networked IP on a Power-Optimized Adaptable Platform
Key Features
Intelligent Engines
Consisting of both AI Engines and DSP Engines, Intelligent Engines support a breadth of workloads common in edge applications including AI inference, image processing, and motion control. AI Engines are a breakthrough architecture based on a scalable array of vector processors and distributed memory, delivering breakthrough AI performance/watt. DSP Engines are based on the proven slice architecture in previous-generation Zynq® adaptive SoCs, now with integrated floating-point support, and are ideal for wireless and image signal processing, data analytics, motion control, and more.
Adaptable Engines
Programmable logic enables the development of custom computational blocks for differentiation, future-proofing, and ever-changing algorithms. Loaded with a wide variety of memory elements and tightly coupled with programmable I/O, the Adaptable Engines allow users to create powerful accelerators for any application.
Scalar Engines
Scalar engines are available for diverse application needs. The application processing unit is ideal for complex applications supported by an OS, and the real-time processing unit is ideal for latency-sensitive applications. A separate platform management controller manages system boot, security, and debug.
112G PAM4 Transceivers
800G Networks and Beyond
The Versal Premium series’ 112G PAM4 transceivers are central to enabling power-optimized, 800G network systems. The Versal Premium ACAP features a broad selection of 32G, 58G, and 112G transceivers on the same device, allowing vendors to scale mainstream 100G systems, ramp 400G deployment, and position themselves for 800G and beyond.
400G High-Speed Crypto Engines
Line Rate Encryption for Secure Networks
The Versal Premium ACAP delivers 1.6Tb/s of line rate encryption throughput, making it an ideal platform for secure networks. It features the world’s only hardened 400G channelized High-Speed Crypto (HSC) Engines in an adaptable platform. The HSC Engine supports the AES-GCM encryption/decryption, MACsec, and IPsec for multi-layered security.
Multirate Ethernet Cores with FEC
Single Platform for 10G to 800G
The dedicated connectivity IP enables secure multi-terabit Ethernet with support for many data rates and protocols. The mix of 100G and 600G Ethernet cores delivers up to 5Tb/s of throughput and allows scalability from the access network to metro to core, all on a single platform.
600G Interlaken with FEC
Scalable Chip-to-Chip Interconnect
Integrated Interlaken cores in the device support up to 600Gb/s with built-in flow control for reliable, high-bandwidth data transmission. With integrated RS-FEC for power-optimized error correction, Versal Premium devices support scalable chip-to-chip interconnect while minimizing the I/O and power overhead for networking systems.
PCIe Gen5 with DMA & CCIX, CXL
Optimal CPU-to-Accelerator Communication
PCIe® Gen5 accelerates server CPU-to-accelerator communication for next-generation compute applications, while the hardened DMA engines with programmable NoC deliver scalable and turn-key virtualization for workload provisioning and deployment. The CCIX/CXL sub-blocks enable (a)symmetric communication for diverse cloud topologies.
Programmable Network on Chip
Guaranteed QoS and Power Efficiency
The programmable network on chip (NoC) provides an optimized multi-terabit interconnect between the different compute engines and integrated IP blocks in the Versal ACAP, simplifying timing closure and saving logic resources. The NoC compiler provides a streamlined programming experience while allowing users to manage latency and QoS for critical datapaths.
Find Out More
Solving a broad range of industry-specific problems with performance and flexibility
Phased Array Radar
Adaptive beamforming for phased radar array performs precision tracking and guidance in a spectrum contested environment. Versal® Premium devices with AI Engines enable 4X greater signal processing capacity1 than the previous generation, allowing designers to implement more compute-intensive functions beyond beamforming. AI Engines and DSP Engines natively support various data types, including highly efficient single-precision floating-point for greater dynamic range, which is critical in radar applications.
The Versal Premium series provides 112G PAM4 transceivers with power-optimized IP to ensure secure networking from antennas to backend interfaces while easing system integration and lowering latency and power. The innovative, heterogeneous integration in the Versal architecture results in industry-leading reductions in size, weight, and power (SWaP) advantage for many radar system designs.
1: Total equivalent DSP engine capacity vs. Virtex® UltraScale+™ VU13P FPGA
Metro/Core Transport Networks
Due to fast-growing bandwidth demands for 5G wireless, xHaul, PON, and cable access, there is tremendous pressure on the metro/transport networks to aggregate and intelligently process network traffic. Versal® Premium series provide 112G PAM4 transceivers with dedicated connectivity IP such as 600G channelized multirate Ethernet and integrated 600G Interlaken with FEC to enable thermally efficient designs in complex metro/core transport networks.
With double the compute density of traditional hardware programmable devices, Versal Premium enables hardware differentiation, adaptability to evolving standards, and the ability to infuse AI/ML for tomorrow’s autonomous and intelligent networks.
Scalable Acceleration in the Data Center
As a heterogeneous platform, Versal Premium features the world’s highest compute density for adaptable cloud acceleration for a breadth of workloads, including genomics, video transcoding, search, and machine learning.
Dynamic function eXchange (DFX) allows users to swap compute kernels in milliseconds to provision accelerators for the most efficient use of cloud infrastructure. With massive on-chip memory capacity and bandwidth and double the compute density of currently deployed FPGA accelerators, Versal Premium offers superior compute and streamlined orchestration.
Built from the ground up to seamlessly integrate with cloud infrastructure, Versal Premium features an integrated shell that ensures host server and system memory communication is available at boot, allowing accelerator designers to spend less time on connectivity and more time on differentiation.
Data Center Interconnect
As data centers scale, data center interconnect (DCI) technologies must evolve to enable high capacity, scalability, and power efficiency. Versal Premium series allows service providers to deploy flexible transport technology by providing scalable transceivers up to 112G, up to 5Tb/s of ethernet throughput, and 1.6Tb/s of line-rate encryption for fast and secure connectivity between data centers.
Test & Measurement
To pioneer network technologies from data center to 5G, vendors need to leverage bleeding-edge communication test equipment to ensure interoperability and robust network traffic management. AI Engines and DSP Engines in the Versal Premium series provide industry-leading signal processing performance and logic capacity to implement the most complex test logic for automated test, data-flow control, tracking, and reporting.
112G PAM4 transceivers have integrated KP4 FEC for emerging protocols as well as interoperability with optics and backplanes. Dedicated channelized multirate Ethernet cores with aggregate throughput of 5Tb/s feature modularly accessible MAC, PCS, and FEC blocks alongside programmable logic resources for custom error injection and statistical analysis.
Versal® Premium Series Features Overview
Scalar Engines Features
| VP1002 | VP1052 | VP1102 | VP1202 | VP1402 | VP1502 | VP2502 | VP1552 | VP1702 | VP1802 | VP2802 | |
|---|---|---|---|---|---|---|---|---|---|---|---|
| Application Processing Unit | Dual-core Arm® Cortex® A72, 48KB/32KB L1 Cache w/ parity & ECC; 1MB L2 Cache w/ ECC | ||||||||||
| Real-Time Processing Unit | Dual-core Arm Cortex R5F, 32KB/32KB L1 Cache, and 256KB TCM w/ECC | ||||||||||
| Memory | 256KB On Chip Memory w/ECC | ||||||||||
| Connectivity | Ethernet (x2); UART (x2); CAN FD (x2); USB 2.0 (x1); SPI (x2); I2C (x2) | ||||||||||
Intelligent Engines Features
| VP1002 | VP1052 |
VP1102 | VP1202 | VP1402 | VP1502 | VP2502 | VP1552 | VP1702 | VP1802 | VP2802 | |
|---|---|---|---|---|---|---|---|---|---|---|---|
| AI Engines | - | - | - | - | - | - | 472 |
- | - | - | 472 |
| DSP Engines | 1,140 | 1,572 | 1,904 | 3,984 | 2,672 | 7,440 | 7,392 | 7,392 | 10,896 | 14,352 | 14,304 |
Adaptable Engines Features
| VP1002 | VP1052 | VP1102 | VP1202 | VP1402 | VP1502 | VP2502 | VP1552 | VP1702 | VP1802 | VP2802 | |
|---|---|---|---|---|---|---|---|---|---|---|---|
| System Logic Cells (K) | 833 | 1,186 | 1,575 | 1,969 | 2,233 | 3,763 | 3,738 | 3,837 | 5,558 | 7,352 | 7,326 |
| LUTs | 380,800 | 542,080 | 719,872 | 900,224 | 1,020,928 | 1,720,448 | 1,708,672 | 1,753,448 | 2,540,672 | 3,360,896 | 3,349,120 |
Foundational Platform Features
| VP1002 | VP1052 | VP1102 | VP1202 | VP1402 | VP1502 | VP2502 | VP1552 | VP1702 | VP1802 | VP2802 | |
|---|---|---|---|---|---|---|---|---|---|---|---|
| GTY Transceivers (32.75Gb/s) | 20 | 20 | - | - | - | - | - | - | - | - | |
| GTYP Transceivers1 (32.75Gb/s) | - | - | 8 | 281 | 8 | 281 | 281 | 681 | 281 | 281 | 281 |
| GTM Transceivers (58G (112G)) | 24 (12) | 48 (24) | 64 (32) | 20 (10) | 96 (48) | 60 (30) | 60 (30) | 20 (10) | 88 (44) | 140 (70) | 140 (70) |
| CCIX & PCIe® w/DMA (CPM4) | 2 x Gen4x4 | 2 x Gen4x4 | - | - | - | - | - |
- | - | - | - |
| CCIX & PCIe® w/DMA (CPM5) | - |
- |
- | 2 x Gen5x8, CCIX | - |
2 x Gen5x8, CCIX | 2 x Gen5x8, CCIX | 2 x Gen5x8, CCIX | 2 x Gen5x8, CCIX | 2 x Gen5x8, CCIX | 2 x Gen5x8, CCIX |
| PCI Express® with CXL | 1 x Gen4x8 | 1 x Gen4x8 | 2 x Gen5x4 | 2 x Gen5x4 | 2 x Gen5x4 | 2 x Gen5x4 | 2 x Gen5x4 | 8 x Gen5x4 | 2 x Gen5x4 | 2 x Gen5x4 | 2 x Gen5x4 |
| 100G Multirate Ethernet MAC | 3 | 5 | 6 | 2 | 6 |
4 | 4 | 4 | 6 | 8 | 8 |
| 600G Ethernet MAC | 2 | 3 | 7 | 1 | 11 | 3 | 3 | 1 | 5 | 7 | 7 |
| 600G Interlaken | 1 | 2 | 0 | 0 | 0 | 1 | 1 | 0 | 2 | 3 | 3 |
| 400G High-speed Crypto Engines | 1 | 1 | 3 | 1 | 4 | 2 | 2 | 2 | 3 | 4 | 4 |
1. 16 GTYP transceivers are dedicated to the CPM5 for PCI Express use
Documentation
Versal Design Guidance and Documentation
Xilinx provides a breadth of documentation, resources, and methodologies to accelerate your development on the Versal architecture. If you’re not sure where to begin with Versal ACAPs, the Design Flow Assistant is an interactive guide to help you create a development strategy, while the Design Process Hubs are a visual and streamlined reference to all Versal documentation by design process.
Integrated Software and Hardware Platform for All Developers
With an inherently software programmable silicon infrastructure, the Versal® ACAP is designed from the ground up to be software-centric. The enhanced Xilinx® Vivado® ML Editions introduces a new system design methodology and development environments such as traffic analyzer, NoC compiler, data flow modeling, and more. A high-speed, unified, cohesive debug environment accelerates debug and trace across Scalar, Adaptable, and Intelligent engines.
Download Vivado ML Editions >
The Xilinx Vitis™ unified software platform provides comprehensive core development kits, libraries that use hardware-acceleration technology. The platform provides an efficient, convenient, and unified software environment from the cloud to the edge. As a proud member of the open source community, the Vitis unified software platform is entirely free and open source.
Download Vitis Unified Software Platform >
Start Prototyping using Versal ACAP Evaluation Kits
Designers who are targeting a Versal® Premium device can get started now with the Versal Prime Series VMK180 Evaluation Kit and Versal AI Core VCK190 Evaluation Kit. Versal Premium devices are based on the same architecture as the Versal Prime series and Versal AI Core series.
The evaluation kits have everything you need to jump-start your design, including the ability to perform system testing, evaluate key interfaces, and adopt the ACAP design methodology.
Buy the Versal AI Core Series VCK190 Evaluation Kit for AI Engines >
Buy the Versal Prime Series VMK180 Evaluation Kit for other common architectural blocks >
Versal Premium series evaluation kits are currently in early access. Contact your local AMD Xilinx sales representative to apply for the early access program or click the Contact Sales link on the VPK120 product page.
Learn more about the Versal Premium Series VPK120 Evaluation Kit >
Training Courses
Xilinx training and learning resources provide the practical skills and fundamental knowledge you need to be fully productive in your next development project.
Getting Started with the Xilinx Versal ACAP Platform
Designing with the Versal ACAP: Architecture and Methodology
Designing with the Versal ACAP: Programmable Network on Chip
Designing with the Versal ACAP: Power and Board Design
Designing with Versal AI Engine 1 - Architecture and Design Flow
Designing with Versal AI Engine 2 - Graph Programming with AI Engine Kernels
Designing with Versal AI Engine 3 - Kernel Programming and Optimization
Versal Design Guidance and Documentation
Xilinx provides a breadth of documentation, resources, and methodologies to accelerate your development on the Versal architecture. If you’re not sure where to begin with Versal ACAPs, the Design Flow Assistant is an interactive guide to help you create a development strategy, while the Design Process Hubs are a visual and streamlined reference to all Versal documentation by design process.
