XQR Kintex™ UltraScale FPGAs are high-performance monolithic FPGAs with a focus on performance. High DSP and block RAM-to-logic ratios and next-generation transceivers combined with space-grade packaging to handle vibration and handling requirements for launch and operation enable a new generation of high-density FPGAs for on-orbit reconfiguration targeted for applications like on-board processing, digital payloads, remote sensing, and many more.
|RT Kintex UltraScale
|Memory (Mb)||4.1 to 9.9||12.3||38|
|System Logic Cells (k)||55 to 200||131||726|
|CLB Flip-Flops (k)||49.1 to 178.1||81.9||663|
|CLB LUTs (k)||49.1 to 178.1||81.9||331|
|MGTs||None||18 at 4.25Gbps||32 at 12.5 Gbps|
|User I/O||640 to 960||836||620|
|DSP Slices||32 to 192||320||2,760|
|Radiation (TID, SEL)||300, >125||1,000, >125||100, >80|
|Reliability (Package, Test)||CNA1509; V-Flow||CNA 1752; B-Flow & V-Flow||CNA 1509; B-Flow & Y-Flow|
The space-grade XQR UltraScale™ architecture-based devices extend the benefit of commercial silicon with unique ceramic column grid array package, tested to stringent qualification flows like AMD B, Y test flows (QML compliant), full military operating temperature range support, and radiation tested for single-event effects. RT Kintex UltraScale device uses more than 40 proprietary, patented circuit design and layout techniques to reduce the SEU cross-section. The table below lists radiation characteristics for RT Kintex UltraScale.
|TID||Total Ionized Dose (GEO)||-||100||120||Krad (Si)|
|SEUCRAM||Single-Event Upset in Configuration RAM (GEO)||-||1.0e-8||-||Upset/bit/day|
|SEUBRAM||Single-Event Upset in Block RAM (GEO)||-||8.5e-9||-||Upset/bit/day|
|SEFICRAM||Single Event Functional Interrupt Orbital Upset Frequency – Configuration RAM (GEO)||-||4.5e-4||-||Upset/device/day|
The following table describes the types of Single Event Effects. For detailed reports visit the Space Lounge.
|Radiation Type||Radiation Signature||Target/Comments|
|Single Event Upset (SEU)||Corruption of the information stored in a memory element||Memories, latches in logic devices. Composed of single bit upsets (SBU) or multiple bit upset (MBU).|
|Single Event Transient (SET)||Impulse response of certain amplitude and duration||Analog and mixed-signal circuits. Can lead to SEU if latched in memory cell.|
|Single Event Latchup (SEL)||High-current conditions||CMOS devices. Might lead to hard failure.|
|Single Event Functional Interrupt (SEFI)||Corruption of a datapath leading to loss of normal operation||Complex devices with built-in state machine/control sections or systems.|