Optimized for high-performance logic, Virtex®-4 LX FPGAs are a pin-compatible member of the world’s first 90nm family fabricated in 1.2v, triple-oxide process technology.
Defense-grade Virtex-4Q LX FPGAs Benefits
Up to 200,000 logic cells
Compact utilization for reduced device cost
Configurable as logic, RAM, or shift registers
500 MHz Smart RAM Hierarchy
Configure multi-rate FIFO from block RAM without consuming logic resources
Block RAM with built-in Error Checking and Correction (ECC) for high-reliability systems
Integrated source-synchronous support for easy interfaces to external memory
New ChipSync™ source-synchronous technology simplifies board design
Enhanced clocking helps you to achieve highest performance
Virtex-4 FPGAs incorporate advanced clocking capabilities that help you to achieve highest performance by minimizing clock jitter, skew, and duty cycle distortion.
Abundant clock resources
32 clock inputs (differential or single-ended)
32 global clock networks
16-48 regional clock networks
8-24 distinct clock regions
Abundant clock management features
Up to 20 Digital Clock Managers (DCMs)
Up to 8 Phase Matched Clock Dividers (PMCDs)
32 Global Clock Buffers
High Performance
500 MHz clocking throughout the chip
30% reduction in jitter
Automatic duty cycle precision
Easy design
Quadrant and buffer restrictions eliminated
Enhanced Clocking Wizard for design generation
New automatic jitter and skew reporting for timing budgets
Digital Clock Managers (DCM)
Clock deskew
Delay-locked loop (DLL) completely eliminates clock distribution delays
Phase shift control
Coarse (quadrature) phase shifting
Fixed and variable fine-grained phase (1/256 clock period) shifting modes for clock/data synchronization
Direct DCM phase-shift control for advanced applications
Flexible frequency generation from 24 MHz to 500 MHz
Integer multiplication and division parameters
Dynamic reconfiguration of DCM multiply, divide, and phase shift
Two performance modes
Maximum Speed - maximum frequency, minimum jitter
Maximum Range - minimum frequency, widest phase shift range, lowest power
Phase-Matched Clock Dividers (PMCD)
A Virtex-4 clock management enhancement, PMCDs provide improved handling of multiple synchronous clock domains.
Phase-matched divided clocks
Create up to four frequency-divided and phase-matched versions of an input clock
Divide by 1, 2, 4 or 8
Divided clocks are rising-edge aligned
Phase-matched delayed clocks
Preserve edge alignments and phase relations between the divided clocks and other clocks
This fourth-generation RocketIO™ GTP transceiver technology delivers flexible SERDES with 100 Mbps-to-3.75 Gbps operating range that supports all popular protocols.
Cross platform pin compatibility eases design upgrades to GTX transceivers for higher line rates
Lowest power consumption in the industry: less than 100 mW per channel at 3.2 Gbps
Multiple protocols (standard and custom) can be implemented in a single FPGA.
Compliance with popular standards and protocols for chip to chip, backplanes and optical device interfaces
Advanced Tx / Rx equalization techniques to drive backplanes and other difficult channels
Built-in PRBS generator/checker accelerates debug
Works seamlessly with integrated PCI Express® endpoint and tri-mode Ethernet MAC blocks
Connect to the Internet via an integrated tri-mode EMAC
Virtex®-4 FX FPGAs include built-in Ethernet connectivity with up to four Ethernet media access controller (MAC) blocks. The Xilinx unique tri-mode Ethernet MAC provides guaranteed performance and UNH-verified interoperability. This integrated functionality reduces total system cost by reducing design and verification effort, freeing approximately 1,800 logic cells per Ethernet MAC in the FPGA fabric. Plus reduced component count, and simpler board design.
550 MHz block RAM for high-density embedded memory
The Virtex-4 FX platform FPGAs provides up to two PowerPC® 405, 32-bit RISC processor cores in a single device. These industry standard processors offer high performance and a broad range of third-party support. The new Auxiliary Processor Unit (APU) controller simplifies the integration of hardware accelerators and co-processors.
The DSP slice forms the basis of a versatile, coarse grain DSP architecture, enabling you to efficiently add powerful FPGA-based DSP functionality to your system.
DSP Slices have been custom designed in silicon to achieve 500 MHz performance independently or when combined together within a column to implement DSP functions.
Each DSP Slice draws only 2.3 mW/100 MHz, at a typical toggle rate of 38%, just 6% of the power consumption of previous FPGA DSP implementations.
The DSP Slice supports over 40 dynamically controlled operating modes including; multiplier, multiplier-accumulator, multiplier-adder/subtractor, three input adder, barrel shifter, wide bus multiplexers, or wide counters.
Cascade DSP Slices without using FPGA fabric or routing resources to perform wide math functions, DSP filters, and complex arithmetic.
Architectural highlights of the DSP slices:
18-bit by 18-bit, two's complement multiplier with full precision 36-bit result, sign extended to 48 bits.
Three input, flexible 48-bit adder/subtracter with optional registered accumulation feedback.
Over 40 dynamic user-controller operating modes to adapt XtremeDSP slice functions from clock cycle to clock cycle.
Cascading, 18-bit B bus, supporting input sample propagation.
Cascading, 48-bit P bus, supporting output propagation of partial results.
Multi-precision multiplier and arithmetic support with 17-bit operand right shift to align wide multiplier partial products (parallel or sequential multiplication).
Symmetric intelligent rounding support for greater computational accuracy.
Performance-enhancing pipeline options for control and data signals are selectable by configuration bits.
Input port "C" typically used for multiply, add, large three-operand addition or flexible rounding mode.
Separate reset and clock enable for control and data registers
ExpressFabric architecture for efficient, high-performance logic
Protect your intellectual property with security you can bank on. Virtex™-4 FPGAs protect your design with AES (Advanced Encryption Standard) technology-the same technology used by financial institutions worldwide.
Features at a Glance
Software-based bitstream encryption and on-chip bitstream decryption logic with dedicated memory for storing the 256-bit encryption key.
You generate the encryption key and encrypted bitstream using Xilinx ISE™ software. During configuration, the Virtex-4 device decrypts the incoming bitstream.
Battery-backed key provides unbreakable security
The Xilinx approach to security makes it virtually impossible for thieves to steal your design data. Virtex-4 FPGAs store the encryption key internally in dedicated RAM, backed up by a small externally connected battery (typical life 20+ years). It is not possible to read the encryption key out of the device. In contrast to protection schemes that use non-volatile key storage, any attempt to remove the Virtex-4 FPGA from the board in order to decapsulate the package for probing results in the instant loss of your encryption key and programming data.
Designing with Secure Chip AES
Encrypt your design data with the iMPACT configuration tools included in ISE software
