The Virtex-4 FX platform FPGAs provides up to two PowerPC® 405, 32-bit RISC processor cores in a single device. These industry standard processors offer high performance and a broad range of third-party support. The new Auxiliary Processor Unit (APU) controller simplifies the integration of hardware accelerators and co-processors.

Embedded PowerPC 405 (PPC405) core

• Embedded 450 MHz, 700+ DMIPS RISC core (32-bit Harvard architecture).
• 5-stage data path pipeline.
• Hardware multiply and divide.
• 32 x 32-bit general-purpose registers.
• 16 KB 2-way set-associative instruction and data caches.
• Memory Management Unit (MMU) enables RTOS implementation.
• 64-entry unified Translation Look-aside Buffers (TLB).
• Variable page sizes (1KB - 16 KB).
• Enhanced instruction and data On-Chip Memory (OCM) controllers interface directly to embedded Block RAM.
• Supports IBM CoreConnect bus architecture.
• Debug and trace support.

New Auxiliary Processor Unit (APU) controller interfaces the CPU pipeline directly to the FPGA fabric

• Enables Hardware Accelerators.
• Supports User Defined Instructions.
• Supports up to four 32-bit word data transfers in a single instruction.
• Floating point and co-processor support.
• Supports autonomous instructions: no pipeline stalls.
• 32-bit instruction and 64-bit data.
• 4-cycle cache line transfer.

Provides direct interface to Tri-mode Ethernet MAC configuration registers