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Defense-grade Virtex-6Q SXT FPGAs

Optimized for systems requiring ultra-high performance DSP with low-power 6.6Gbps serial connectivity, Virtex®-6Q SXT defense-grade FPGAs deliver the highest ratio of DSP and memory resources.

Defense-grade Virtex-6Q SXT FPGAs Benefits

  • Build efficient hardware implementations of filters and other complex functions by leveraging the FPGA inherent parallelism
  • Virtex-6 SX475T FPGAs deliver more than 1,000 GMACS (1 x 1012 Multiply-Accumulates per Second) with 2,016 DSP48E1 slices
  • Virtex-6 SXT FPGAs offer the highest ratio of Block RAM for memory intensive applications: more than 38 Mbits in Virtex-6 SX475T FPGAs
  • Enhanced DSP48E1 slice architecture with a 25-bit pre-adder, 25 x 18 multiplier, 48-bit adder, and 48-bit accumulator (cascadable to 96 bits) enables high performance filters with fewer slices
  • Low power consumption: each DSP48E1 slice draws only 1.09mW/ 100MHz at a 38% toggle rate, a 20% reduction from previous-generation slices
  • Flexible multi-rate GTX transceivers support line rates from 150Mbps to 6.6Gbps with low power consumption: <150mW (typ) at 6.6Gbps
  • Integrated PCI Express® interface blocks provide Gen 1 and Gen 2 connectivity (x1, x2, x4, x8)
  • Integrated tri-mode Ethernet media access controller (MAC) blocks provide IEEE 802.3 compliant 10/100/1000 Mbps connectivity, plus a 2.5Gbps mode for higher bandwidth using custom protocols
  • Implement Serial RapidIO with Xilinx soft IP
  • Xilinx provides flows and IP tailored to the needs of algorithm, system, and hardware developers with ISE® Design Suite
  • Achieve greater designer productivity with a flow that extends widely popular MATLAB and Simulink® modeling environments for FPGA design and includes System Generator for DSP™ and the AccelDSP™ synthesis tool
  • Achieve breakthrough performance, power, and cost benefits with an optimized, bit and cycle accurate library for assembling sophisticated signal processing systems

Virtex-6Q FPGA Features

Features LXT SXT
40nm ExpressFabric™ architecture with 6-input LUTs
600MHz clock management tiles (2 MMCM) 6 - 18 12 - 18
600MHz block RAM (1,000Kbits) 5.6 - 25.9 25.3 - 38.3
1.40Gbps SelectIO with ChipSync technology
6.6Gbps GTX transceivers 12 - 36 12 - 36
11.18Gbps GTH transceivers - -
PCI Express ( PCIe ) Endpoint/Root Port blocks 1 - 2 2
Ethernet Media Access Controller blocks 4 4
600MHz DSP48E1 slices 288 - 864 1,344 - 2,016
System monitor and analog-to-digital converter
Third-generation sparse chevron packaging technology
Enhanced configuration and bitstream protection

What applications is this good for?

Possible applications include

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