Breakthrough Performance and Integration
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Up to 48 transceivers running up to 58Gb/s PAM4 for multi-terabit systems and up to 32 transceivers operating at 32.75Gb/s for 25G interoperability
28G and 58G backplanes, 32.75Gb/s and 58Gb/s of chip-to-chip, and chip-to-optics support
Superior high-quality signal for 50/100/200/400G optics and protocols via enhanced continuous adaptive RX equalization and built-in KR-FEC
Up to 38 TOPs (22 TeraMACs) of DSP compute performance for diverse applications in the data center
Eliminating discrete ICs for Ethernet, gearboxes, memory, and PCIe enables small footprint system design without comprising performance
PCIe® Gen3x 16 in all devices and PCIe Gen4x 8 with CCIX support in select devices enable complete end-to-end solutions that support multi-100G ports
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Due to rapidly growing bandwidth demands for 5G, PON, cable access, and metro & transport networks have been under pressure to deliver aggregated network traffic to core networks. Virtex UltraScale+ 58G FPGAs provide 58G PAM4 transceivers with dedicated 100G MAC IP to allow designers to build flexible equipment with higher port density and greater throughput. With programmability, Virtex UltraScale+ 58G PAM4 FPGAs enable custom logic and the ability to add AI/ML for smart transport networks, so that network equipment providers (NEPs) can focus on end-product innovation and differentiation while reducing time-to-market and total cost of ownership.
Signal analysis equipment, such as spectrum/network analyzers, requires more extensive signal processing power and high I/O bandwidth. Virtex UltraScale+ 58G PAM4 FPGAs provide UltraRAM for data staging and block RAM for coefficient tables and FIFOs. With a significantly large number of DSP blocks and 80 high-speed transceivers available in the FPGA, test and measurement platform designers can build a high-performance system with flexibility and scalability.
With the integrated PAM4 transceivers in Virtex UltraScale+ 58G PAM4 FPGAs, SmartNIC designers can eliminate gearboxes and simplify designs. PCIe Gen4 support dramatically increases a server’s data handling capacity and enhances performance by offering acceleration capability while alleviating the I/O bottlenecks. Furthermore, FPGAs span a comprehensive range of workloads, which allows SmartNICs built with Virtex UltraScale+ 58G PAM4 FPGAs to add and blend workloads across compute, network, and storage, dynamically changing functionality without compromising connectivity.
As data centers scale, data center interconnect technologies must evolve to enable high capacity, scalability, and power efficiency. To address the demand for high-performance connectivity between data centers, Virtex UltraScale+ 58G PAM4 FPGAs provide high-speed I/O throughput by supporting the new optics and protocols with superior port density and performance-per-watt.
Converged access fronthaul gateways are one of the keys to delivering a cost-effective 5G buildout and service delivery. Thanks to the programmability of Virtex UltraScale+ FPGAs, these gateways can serve multiple functions and enable several services to be carried across a single interface such as Ethernet, FlexE, and optical transport networks (OTNs). With 58G PAM4 transceivers, fronthaul gateways support multi-100G interfaces with new optics to optimize transport costs. Virtex UltraScale+ 58G PAM4 FPGAs provide the path to a single converged gateway function for service providers looking to save cost and add significant flexibility to their evolving 4G and 5G access networks.
The explosion of data in modern applications strains storage infrastructure, with bandwidth requirements increasing rapidly while power and form factor constraints remain fixed. For next-generation storage systems, FPGAs are ideal for delivering improved performance in systems with RDMA and NVMe over Fabrics (NVMe-oF) offloads, either integrated as SSD controllers or in hyperconverged infrastructure to handle complex storage processing tasks. With integrated 58G PAM4 transceivers, small package options, and PCIe Gen4 IP, Virtex UltraScale+ 58G PAM4 FPGAs enable the increased acceleration of a variety of storage workloads including data compression, decompression, deduplication, or sequencer functionality while improving overall storage utilization and minimizing the burden on the CPU.
|System Logic Cells (K)
|GTY/GTM Transceivers (32.75/58Gb/s)
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